FSM Synthesis · synthesis | DenseChip

Part 4 · Sequential, FSM and Memory · Intermediate

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FSM synthesis turns a state register plus next-state logic into flops and gates. The coding style decides what the tool recognises, the encoding trades area against speed, and unreachable states need a recovery plan.

Choice	Options	What it trades
Coding style	One-, two- or three-process	Readability against how cleanly the tool sees the state register.
State encoding	Binary, one-hot or gray	Flop count against decode depth and switching activity.
Recovery	Default arc, reset, or validity check	Safety against extra next-state logic.
Outputs	Mealy, Moore, or registered	Response latency against output timing.

Lesson	What it covers
Coding styles	One-, two- and three-process forms and what each infers.
State encoding	Binary, one-hot and gray with the area, speed and power trade-off.
Unreachable states	Invalid codes and default recovery to a safe state.
Output registering	Mealy and Moore outputs and why registering outputs helps timing.
Yosys FSM passes	How fsm_detect, fsm_extract and fsm_recode handle an FSM.

Check yourself Why does a one-hot FSM need safe recovery even though its states are all defined?

Faults and uninitialised flops can land the machine in an all-zero or multi-hot state no case item covers. Without a default recovery arc it never returns.

Related topics

Up nextCoding Styles

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