Flops, Resets and Enables · synthesis

Part 4 · Sequential, FSM and Memory · Intermediate

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Sequential RTL infers one flop family per idiom: plain, enabled, and synchronous or asynchronous reset. Each family is a distinct generic cell ($dff, $dffe, $sdff, $adff); whether that yields a distinct library cell depends on the library.

RTL idiom	Generic cell	In course.lib
`always @(posedge clk) q <= d;`	`$dff`	`DFF` (area 8)
`if (en)` around the load	`$dffe`	`DFF` plus feedback logic; no clock-enable cell here
Reset tested inside the clocked block	`$sdff`	Mapping varies by library
Reset in the sensitivity list	`$adff`	`DFFR` (area 10)

From RTL idiom to library cells.

Each RTL idiom infers one generic flop cell, which then maps to library cells plus logic.

Lesson	What it covers
D Flop Inference	The plain clocked block and the single `$dff` cell it infers.
Enables: Mux or Clock Enable	Enabled flops infer `$dffe`, built from a mux or a clock-enable cell.
Synchronous and Asynchronous Reset	Sync reset gives `$sdff` and async reset gives `$adff`, with set alike.
Reset-less Flops and Initial Values	Why datapath flops skip reset, and what initial values really mean.
Mapping Flops to Library Cells	From generic cells to `DFF` and `DFFR` with `dfflibmap`, plus scan.

Check yourself A block loads q only when en is high and has no reset. Which generic cell does it infer?

An enabled flop without reset: $dffe. The enable selects between the new data and the held value.

Up nextD Flop Inference

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