Retiming and Pipelining · synthesis

Part 4 · Sequential, FSM and Memory · Intermediate

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Retiming moves registers across combinational logic to balance stage delays. It keeps the steady-state output stream and per-path latency.

Reset-cycle outputs and the initial-state flush can still change and must be rechecked. Pipelining adds registers to split long paths, which adds latency.

Retiming balancing two uneven stages into two even stages.

Retiming shifts one block across the register: stages 8 and 4 ns become 6 and 6 ns.

Lesson	What it covers
What retiming moves	Forward and backward register moves across gates and fanout, with a balanced pair.
Latency, throughput and register count	Why latency stays fixed while throughput rises, and when the register count changes.
Reset, initial state and equivalence	Reset-cycle differences after a move and what equivalence can still show.
Pipelining a long path by hand	Cutting a 12 ns path into three stages with valid bits and a testbench.
A retiming model and the tool flow	A small Python stage-graph model plus a sketch of the synthesis tool flow.

Check yourself Two stages take 8 ns and 4 ns. Retiming balances them to 6 ns and 6 ns. What changed and what did not?

The clock period changed from 8 ns to 6 ns. Latency did not: each input-to-output path still crosses one register.

Up nextWhat Retiming Moves

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Lesson

What it covers

What retiming moves

Forward and backward register moves across gates and fanout, with a balanced pair.

Latency, throughput and register count

Why latency stays fixed while throughput rises, and when the register count changes.

Reset, initial state and equivalence

Reset-cycle differences after a move and what equivalence can still show.

Pipelining a long path by hand

Cutting a 12 ns path into three stages with valid bits and a testbench.

A retiming model and the tool flow

A small Python stage-graph model plus a sketch of the synthesis tool flow.