Pipelining inserts registers into combinational logic. Unlike retiming, it adds latency: each new register stage adds one cycle.
The cut points should balance the stages. The slowest stage sets the period, so an uneven split wastes the faster stages.
Every data register needs a matching valid bit. The valid bit shifts alongside the data and says which stages hold real results.
After reset all valid bits are clear. The first real result exits after as many cycles as there are new stages.
Take a 12 ns EXAMPLE path of blocks 5, 4 and 3 ns. Insert two registers to make three stages.
EXAMPLE delays with register overhead t_cq = 0.3 ns and t_su = 0.2 ns
before: T = 12 + 0.3 + 0.2 = 12.5 ns, EXAMPLE frequency = 1 / 12.5 ns = 80 MHz
after: stages 5, 4, 3 ns, T = max(5, 4, 3) + 0.3 + 0.2 = 5.5 ns
EXAMPLE frequency = 1 / 5.5 ns = 181.82 MHz
speedup = 12.5 / 5.5 = 2.27x, added latency = 2 cyclesStage | Logic (ns) | Stage with overhead (ns) |
|---|---|---|
1 | 5 | 5.5 |
2 | 4 | 4.5 |
3 | 3 | 3.5 |
The slowest logic stage is 5 ns, so the period is 5.5 ns. The split adds two cycles of latency for a 2.27x faster clock.
The two-stage pipeline below computes (a + b) x (c + d) with a two-cycle valid delay. The testbench drives 64 patterns plus a 2-cycle flush and checks every valid output against the direct sum of products.
module pipe2 (
input logic clk,
input logic rst_n,
input logic [3:0] a,
input logic [3:0] b,
input logic [3:0] c,
input logic [3:0] d,
input logic v_in,
output logic [9:0] y,
output logic v_out
);
logic [4:0] s1, s2;
logic [4:0] q1, q2;
logic v1, v2;
assign s1 = {1'b0, a} + {1'b0, b};
assign s2 = {1'b0, c} + {1'b0, d};
always_ff @(posedge clk or negedge rst_n) begin
if (!rst_n) begin
q1 <= '0;
q2 <= '0;
y <= '0;
v1 <= 1'b0;
v2 <= 1'b0;
end else begin
q1 <= s1;
q2 <= s2;
y <= q1 * q2;
v1 <= v_in;
v2 <= v1;
end
end
assign v_out = v2;
endmodule
No. The period follows the slowest stage, so the 5 ns stage plus overhead sets 5.5 ns regardless.
That stage claims valid data while holding reset values. The checker compares garbage and reports a mismatch.