Latency is cycles, throughput is rate

Latency counts register stages from input to output. Throughput counts results per second after the pipeline fills.

Retiming keeps every path register count, so latency is unchanged. A shorter period then raises throughput at the same latency.

When the count changes

The total register count can still move. Forward moves across fanout duplicate registers, and backward moves across shared gates merge them.

A counted example

Take the balanced pair from the previous lesson. Move its register forward across a two-way fanout instead of across a gate.

path registers before = 1, path registers after = 1, latency = 1 cycle both ways
total registers before = 1, total registers after = 2, change = +1
teaching-library cost: one DFF = 8 area units, added area = 1 x 8 = 8 area units
throughput before = 1 result per 8 ns, after = 1 result per 6 ns

Each branch still crosses one register, so latency is one cycle. The design pays one extra register of 8 teaching-library area units.

Common mistakes

Related topics

• What retiming moves

• Delay models and slack