Memory and Macro Inference · synthesis

Part 4 · Sequential, FSM and Memory · Intermediate

Arrays in RTL become either flop arrays or RAM macros. Size, port count and read style decide which one fits.

Question	Flop array	RAM macro
Best size	Small tables, tens of entries	Large tables, thousands of entries
Read style	Sync or async read	Sync read in most compiled macros
Port count	Many ports stay cheap while the memory is small	One or two ports; more ports cost area fast
Reset	Per-bit reset is natural	No per-bit reset; reset needs a wrapper
Flow	Mapped with the logic	Black box with a timing model plus a wrapper

Flop array or RAM macro decision.

Large tables with few ports and sync reads suit macros; the rest stays flops.

Lesson	What it covers
Flop arrays or RAM macros	Capacity arithmetic and when a table should stay flops.
Read and write port styles	Sync and async reads, write ports, and read-during-write rules.
Byte enables and bypass wrappers	Write masks and bypass wrappers around sync-read RAM.
Compilers, macros and wrappers	Memory compilers, black-box macros, wrappers, and port arithmetic.

Check yourself A 32-entry table of 8-bit values: flops or macro, and why?

Flops. At 256 bits the macro overhead exceeds the flop cost, and a flop array needs no wrapper or timing model.