Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
  • Constraints and Timing15
  • Sequential, FSM and Memory19
    • Flops, Resets and Enables
    • FSM Synthesis
    • Memory and Macro Inference
      • Flop Arrays or RAM Macros
      • Read and Write Port Styles
      • Byte Enables and Bypass Wrappers
      • Compilers, Macros and Wrappers
    • Retiming and Pipelining
  • Datapath Synthesis14
  • Area, Power and Test14
  • Verification, ECO and Handoff15
  • Flows and Debugging15
  • Interview and Judgment11
Loading lesson

‹Memory and Macro Inference
  1. Topics
  2. Logic Synthesis
  3. Sequential, FSM and Memory
  4. Memory and Macro Inference
  5. Flop Arrays or RAM Macros

Part 4 · Sequential, FSM and Memory · Intermediate

Flop Arrays or RAM Macros

Flop arrays versus RAM macros, and when a small table should stay flops.

On this page

    What inference decides

    A synthesis tool turns each RTL array into storage plus access logic. A small array becomes one flop per bit with read muxes and write decode.

    A large array becomes a macro instance instead. The tool does not build the storage from gates; it connects a compiled block.

    Array

    Bits

    Bytes

    Likely result

    32 x 8

    256

    32

    Flops

    64 x 32

    2048

    256

    Flops unless ports are few and sync

    4096 x 32

    131072

    16384 (16 KiB)

    Macro

    Capacity arithmetic

    Capacity is depth times width in bits, divided by eight in bytes. Address bits are the ceiling of log2 of the depth.

    The program below checks three capacities and their address widths.

    example.py
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    11
    12
    13
    14
    15
    16
    17
    18
    19
    20
    21
    22
    23
    24
    25
    26
    27
    28
    29
    30
    31
    32
    33
    34
    35
    36
    import sys
    
    def addr_bits(depth):
        n = 0
        while (1 << n) < depth:
            n = n + 1
        return n
    
    cases = [
        (32, 8, 256, 32, 5),
        (64, 32, 2048, 256, 6),
        (4096, 32, 131072, 16384, 12),
    ]
    
    bad = 0
    for i in range(len(cases)):
        depth, width, want_bits, want_bytes, want_addr = cases[i]
        bits = depth * width
        total_bytes = bits // 8
        abits = addr_bits(depth)
        if bits != want_bits:
            print("FAIL: case " + str(i) + " bits " + str(bits))
            bad += 1
        if total_bytes != want_bytes:
            print("FAIL: case " + str(i) + " bytes " + str(total_bytes))
            bad += 1
        if abits != want_addr:
            print("FAIL: case " + str(i) + " addr " + str(abits))
            bad += 1
        if bits % 8 != 0:
            print("FAIL: case " + str(i) + " not a whole number of bytes")
            bad += 1
    
    if bad != 0:
        sys.exit(1)
    print("PASS: capacity arithmetic holds on 3 memories")

    When flops are the right answer

    Flops win for shallow tables with awkward access. Async reads, many read ports and per-bit resets all point at flops.

    The storage cost is easy to bound. A 16-entry table of 8-bit values holds 128 bits.

    Diagram
    16 entries x 8 bits = 128 storage bits
    course.lib DFF area = 8 area units (teaching library, not a process figure)
    storage area = 128 x 8 = 1024 area units, plus read muxes and write decode
    32 entries x 8 bits = 256 bits -> 256 x 8 = 2048 area units

    That linear growth is the whole argument. Doubling the table doubles the flops, while a macro would amortize its fixed overhead.

    Common mistakes

    Common pitfall

    A large table written as a plain array still synthesizes when no macro is bound: it becomes an enormous flop array with wide read muxes. Bind large tables to macros deliberately instead of discovering the flop array in the area report.

    Interview

    Likely probes: sizing the boundary and defending flops.

    • Capacity is depth times width; address bits are the ceiling of log2 of depth.

    • Flops suit small tables, async reads, many ports and per-bit reset.

    • Macros suit large tables with few sync ports, plus a wrapper.

    Check yourself A 64-entry table holds 32-bit values. How many bits and bytes is that, and how many address bits?

    2048 bits, which is 256 bytes. Six address bits cover 64 entries.

    Check yourself A shallow table needs an async read and per-bit reset. Flops or macro?

    Flops. Most compiled macros offer neither, so the macro would need extra logic that erases its advantage.

    Related topics

    • Next: Read and Write Port Styles

    • Register files

    • Flops, Resets and Enables

    Previous

    62 / 139

    Next: Read and Write Port Styles

    Up next

    Up nextRead and Write Port Styles

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • Byte Enables and Bypass Wrappers
    • Compilers, Macros and Wrappers