A reset value belongs to a register, not to a position in the pipeline. When the register moves, its reset value moves with it.
Logic that sat after the register now sits before it, or the reverse. The reset-time output changes even though the steady stream does not.
Take f(x) = x + 10 and g(x) = 2x as EXAMPLE functions. One register sits between them, and it resets to 0.
Cycle | in | out before | out after |
|---|---|---|---|
0 | 7 | 0 | 20 |
1 | 8 | 34 | 34 |
2 | 9 | 36 | 36 |
3 | 10 | 38 | 38 |
Before the move, reset holds the register at 0, so cycle 0 outputs 2 x 0 = 0. After moving the register back across f, cycle 0 outputs 2 x (0 + 10) = 20.
The streams agree from cycle 1 onward. Only the reset cycle differs, so any comparison must skip it.
Combinational equivalence fails after retiming because register positions differ. Sequential equivalence reasons over several cycles instead, and it must skip the flush cycles.
Gated clocks, clock enables and asynchronous resets block the move in most flows. A register the tool cannot analyze stays where it is.
The register now sits before f instead of after it. Cycle 0 computes g(f(0)), which is 2 x 10 = 20.
Usually not. The enable changes which cycles the register samples, so the move needs enable-aware handling that most flows skip.