Reset costs a pin, routing and area on every flop that carries it. Wide datapaths therefore reset only what correctness needs: state, valid flags and control.
Data registers that are always written before they are read need no reset. Their first useful value comes from a load, not from power-up.
The script below mixes one reset-less bit with one sync-reset bit. It asserts one $dff beside one $sdff, proving the two families coexist in one module.
read_verilog <<EOV
module top(input clk, input rst, input [1:0] d, output reg [1:0] q);
always @(posedge clk) q[0] <= d[0];
always @(posedge clk) if (rst) q[1] <= 1'b0; else q[1] <= d[1];
endmodule
EOV
hierarchy -check -top top
proc
opt
select -assert-count 1 t:$dff
select -assert-count 1 t:$sdff
select -assert-none t:$adff
select -assert-none t:$dffe
log PASS: reset and reset-less flops infer $dff beside $sdffThe program below prices reset against reset-less registers in teaching-library units. Its five self-checks repeat the hand arithmetic exactly.
import sys
DFF = 8.0
DFFR = 10.0
def reg_area(bits, reset):
cell = DFFR if reset else DFF
return bits * cell
checks = [
(reg_area(32, False), 256.0),
(reg_area(32, True), 320.0),
(reg_area(64, False), 512.0),
(reg_area(64, True), 640.0),
(reg_area(64, True) - reg_area(64, False), 128.0),
]
for i in range(len(checks)):
got, want = checks[i]
if abs(got - want) > 1e-9:
print("FAIL: check " + str(i + 1) + " got " + str(got) + " want " + str(want))
sys.exit(1)
print("PASS: reset-less datapath areas match hand arithmetic on 5 checks")course.lib EXAMPLE areas: DFF = 8 units, DFFR = 10 units
64-bit datapath without reset: 64 x 8 = 512 units
64-bit datapath with reset: 64 x 10 = 640 units
saving = 640 - 512 = 128 units = 128 / 640 = 20% of the reset versionAn initial assignment sets the simulation value at time zero. Whether it reaches hardware depends on the target: some FPGA flows honour it while an ASIC flow has no such cell.
A flop with no reset reads unknown (x) in simulation until its first load. Silicon powers up to an unpredictable but resolved 0 or 1, so any bit read before its first write is still a real bug.
128 extra units: 640 with reset against 512 without. The saving is 20% of the reset version.
x on a reset-less data bus for the first cycles, then valid data. Is the design broken?Not necessarily. If the consumer ignores the bus until its valid flag asserts, the x window is harmless. If anything reads it first, that read is a bug.