Two reset idioms

Testing reset inside the clocked block infers a synchronous reset. The reset is then just another data input sampled on the edge.

Adding reset to the sensitivity list infers an asynchronous reset. The flop clears the moment reset asserts, with no clock needed.

What Yosys builds

The first script infers a synchronous-reset flop and pins its family. It asserts one $sdff cell and no other flop type.

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read_verilog <<EOV
module top(input clk, input rst, input d, output reg q);
always @(posedge clk) if (rst) q <= 1'b0; else q <= d;
endmodule
EOV
hierarchy -check -top top
proc
opt
select -assert-count 1 t:$sdff
select -assert-none t:$dff
select -assert-none t:$dffe
select -assert-none t:$adff
log PASS: sync reset flop infers one $sdff cell

The second script infers an asynchronous-reset flop. It asserts one $adff cell and no other flop type.

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read_verilog <<EOV
module top(input clk, input rst, input d, output reg q);
always @(posedge clk or posedge rst) if (rst) q <= 1'b0; else q <= d;
endmodule
EOV
hierarchy -check -top top
proc
select -assert-count 1 t:$adff
select -assert-none t:$dff
select -assert-none t:$dffe
select -assert-none t:$sdff
log PASS: async reset flop infers one $adff cell

Choosing between them

Synchronous reset is timed exactly like data, so it needs no special timing treatment. Its cost is effect latency: nothing happens until the next active edge.

Asynchronous reset acts without a clock, which suits power-on and error recovery. Its release must be synchronized to the clock, or some flops leave reset on different edges.

Common mistakes

An async reset released by combinational logic can stagger across flops. That skew is a functional bug that only some testbenches catch.

Related topics

• Enables: Mux or Clock Enable

• Reset-less Flops and Initial Values

• RTL: Reset Strategies