Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
  • Constraints and Timing15
  • Sequential, FSM and Memory19
    • Flops, Resets and Enables
    • FSM Synthesis
      • Coding Styles
      • State Encoding
      • Unreachable States
      • Output Registering
      • Yosys FSM Passes
    • Memory and Macro Inference
    • Retiming and Pipelining
  • Datapath Synthesis14
  • Area, Power and Test14
  • Verification, ECO and Handoff15
  • Flows and Debugging15
  • Interview and Judgment11
Loading lesson

‹FSM Synthesis
  1. Topics
  2. Logic Synthesis
  3. Sequential, FSM and Memory
  4. FSM Synthesis
  5. Unreachable States

Part 4 · Sequential, FSM and Memory · Intermediate

Unreachable States

Unreachable states, invalid codes, and default recovery to a safe state.

On this page

    Where unreachable states come from

    Reachable states are the codes the reset state can walk to along defined arcs. Every other code the flops can hold is unreachable in normal operation.

    Three sources produce them: codes the encoding never assigns, power-up values before reset asserts, and single-event upsets that flip a state bit. Synthesis may also trim logic for codes it proves unreachable, which changes nothing functionally but removes any accidental safety net.

    Counting invalid codes

    Invalid codes are the bit patterns with no state assigned. Fewer state bits mean fewer places to hide; one-hot pays for its speed with many invalid codes.

    Diagram
    4 states in 2 bits (binary):   2^2 - 4 = 4 - 4 = 0 invalid codes
    4 states in 4 bits (one-hot): 2^4 - 4 = 16 - 4 = 12 invalid codes
    5 states in 3 bits (binary):   2^3 - 5 = 8 - 5 = 3 invalid codes

    Three recovery techniques

    Every technique steers invalid codes back to a safe state, usually the reset state. They differ in what they cost and what faults they catch.

    Technique

    What it adds

    Catches

    Default arc

    A default branch to the safe state

    Any invalid code, in both simulation and gates.

    Reset

    A reset line to the state flops

    Power-up values, but only while reset is asserted.

    Validity check

    A one-hot legality test with a recovery arc

    Multi-hot codes explicitly, at the price of a checker.

    The sketch below is illustrative and does not run: it shows the default-arc pattern used through this topic.

    design.sv
    1
    2
    3
    4
    5
    6
    7
    8
    9
    10
    // not-run: illustrative sketch, no testbench in this lesson
    always_comb begin
      next = state;
      case (state)
        IDLE: if (go) next = WORK;
        WORK: if (fin) next = DONE;
        DONE: next = IDLE;
        default: next = IDLE; // every invalid code recovers
      endcase
    end

    Common mistakes

    Reset alone is not recovery: it fixes power-up but never fires on an in-flight upset. Recovery must live in the next-state logic so it acts every cycle.

    Common pitfall

    Relying on full-case coverage without a default is fragile. The tool may prove some codes unreachable and optimise their logic away, leaving simulation and gates to disagree on what an invalid code does.

    Interview

    Likely probes: count invalid codes for a stated machine, and say where recovery lives.

    • Invalid codes are two to the power of state bits minus the state count.

    • Recovery lives in next-state logic as a default arc, not only in reset.

    • One-hot machines have the most invalid codes and need the default most.

    Check yourself A 4-state one-hot machine has 12 invalid codes. Which fault needs the default arc rather than reset?

    An in-flight bit flip to an all-zero or multi-hot code. Reset already finished long ago, so only the next-state default can steer the machine home.

    Check yourself Binary encoding of the same 4 states has no invalid codes. Is recovery still needed?

    Yes, if upsets or uninitialised flops are in the fault model. All four codes are valid, so a flipped bit lands on a wrong but legal state and the design must tolerate that separately.

    Related topics

    • Up: FSM Synthesis

    • Next: Output registering

    • Flops, Resets and Enables

    Previous

    59 / 139

    Next: Output Registering

    Up next

    Up nextOutput Registering

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • Coding Styles
    • Yosys FSM Passes