Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
  • Constraints and Timing15
  • Sequential, FSM and Memory19
    • Flops, Resets and Enables
    • FSM Synthesis
      • Coding Styles
      • State Encoding
      • Unreachable States
      • Output Registering
      • Yosys FSM Passes
    • Memory and Macro Inference
    • Retiming and Pipelining
  • Datapath Synthesis14
  • Area, Power and Test14
  • Verification, ECO and Handoff15
  • Flows and Debugging15
  • Interview and Judgment11
Loading lesson

‹FSM Synthesis
  1. Topics
  2. Logic Synthesis
  3. Sequential, FSM and Memory
  4. FSM Synthesis
  5. Output Registering

Part 4 · Sequential, FSM and Memory · Intermediate

Output Registering

Mealy and Moore outputs, and why registering outputs helps timing.

On this page

    Mealy and Moore

    A Mealy output depends on state and inputs, so it can answer in the same cycle. A Moore output depends on state alone, so it waits for the state to move first.

    Kind

    Depends on

    Timing shape

    Cost

    Mealy

    State and inputs

    Input-to-output combinational path

    Fast response, harder output timing.

    Moore

    State only

    Flop-to-output path

    One-cycle lag, cleaner timing.

    Registered

    State, held a cycle

    Flop-to-flop path

    Extra cycle of latency, best slack.

    Why registered outputs help

    A registered output breaks the input-to-output path into two flop-to-flop stages. Arrival falls, so slack rises by the same amount.

    Diagram
    EXAMPLE parameters (illustrative): clock 100 MHz, so period 10 ns; downstream setup 0.5 ns
    required = period - setup = 10 - 0.5 = 9.5 ns
    Mealy input-to-output arrival 7 ns (stated EXAMPLE parameter)
    Mealy slack = required - arrival = 9.5 - 7 = 2.5 ns
    registered flop-to-flop arrival 4 ns (clk-to-q 1 ns + comb 2.5 ns + route 0.5 ns, EXAMPLE parameters)
    registered slack = 9.5 - 4 = 5.5 ns; cost: outputs lag one extra cycle

    When to keep Mealy

    Mealy answers without waiting a cycle, which some handshake protocols require. Registering there would break the protocol, not just slow it.

    The middle ground is a Moore output: no input path, no extra register. It keeps single-cycle response to state changes while removing the input-to-output arc.

    Common mistakes

    Common pitfall

    Registering an output changes cycle behaviour, so an old testbench that expects same-cycle answers fails even though the gates are correct. Update the protocol timing first, then re-verify.

    Interview

    Likely probes: Mealy against Moore from a waveform, and the price of registering.

    • Mealy moves with inputs inside a state; Moore moves only on state changes.

    • Registering buys slack equal to the arrival drop, here 3 ns.

    • The price is one cycle of latency, which the protocol must allow.

    Check yourself A Mealy output feeds a downstream flop with 2.5 ns of slack. Registering cuts arrival by 3 ns. What is the new slack?

    5.5 ns. Slack is required minus arrival, so cutting arrival by 3 ns adds exactly 3 ns of slack.

    Check yourself Why can a Moore output still glitch during a state change?

    The state bits skew: binary codes flip several bits that arrive at different times, so the decoded output wobbles until all bits settle. Registering the output removes that wobble too.

    Related topics

    • Up: FSM Synthesis

    • Next: Yosys FSM passes

    • Delay Models and Slack

    Previous

    60 / 139

    Next: Yosys FSM Passes

    Up next

    Up nextYosys FSM Passes

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • Coding Styles
    • State Encoding