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Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
  • Constraints and Timing15
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
  • Area, Power and Test14
  • Verification, ECO and Handoff15
  • Flows and Debugging15
    • Scripted Flows and Regression
    • Debugging QoR
    • Simulation-Synthesis Mismatch
      • Sensitivity Lists and Races
      • Blocking and Non-Blocking Assignments
      • X Pessimism, Optimism, and Init
      • Case Priority and Wildcards
      • Directives, Widths, and Gate Simulation
  • Interview and Judgment11
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‹Simulation-Synthesis Mismatch
  1. Topics
  2. Logic Synthesis
  3. Flows and Debugging
  4. Simulation-Synthesis Mismatch
  5. X Pessimism, Optimism, and Init

Part 8 · Flows and Debugging · Intermediate

X Pessimism, Optimism, and Init

X pessimism and optimism, uninitialised state, and reset and init rules.

On this page

    Optimistic X

    Four-state simulation resolves some unknowns away. 1'bx & 1'b0 is 0, and 1'bx | 1'b1 is 1, by the ordinary truth tables.

    An x in an if condition takes the else branch in simulation. Real hardware holds a 0 or a 1 there, so it may take the path simulation skipped.

    Expression

    Simulation

    Hardware reality

    `x & 0`

    0

    One leg is 0, so the gate agrees

    `x | 1`

    1

    One leg is 1, so the gate agrees

    `if (x)`

    Else branch

    Whichever value the wire really holds

    `x ^ x`

    x

    Always 0: any bit XOR itself is 0

    Pessimistic X

    Elsewhere simulation keeps the unknown. A case with an x selector matches no plain item and falls to default, while the gate takes a concrete branch.

    The program below checks both directions on small values: resolving AND, an x select falling to default, and the self-XOR that hardware always resolves.

    example.py
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    import sys
    
    bad = 0
    
    def check(name, got, want):
        global bad
        if got != want:
            print("FAIL: " + name + " got " + str(got) + " want " + str(want))
            bad = bad + 1
    
    def case_mux(sel, a, b):
        if sel == 0:
            return a
        if sel == 1:
            return b
        return "x"
    
    def and2(a, b):
        if a == 0 or b == 0:
            return 0
        if a == "x" or b == "x":
            return "x"
        return 1
    
    check("x-select-takes-default", case_mux("x", 0, 0), "x")
    check("select-zero", case_mux(0, 0, 1), 0)
    check("select-one", case_mux(1, 0, 1), 1)
    check("optimistic-and", and2("x", 0), 0)
    check("and-x1", and2("x", 1), "x")
    check("and-11", and2(1, 1), 1)
    
    agree = 0
    for a in (0, 1):
        if case_mux("x", a, a) == "x":
            agree = agree + 1
    if agree != 2:
        print("FAIL: agree count got " + str(agree) + " want 2")
        bad = bad + 1
    
    if bad != 0:
        sys.exit(1)
    print("PASS: pessimistic select and optimistic AND agree on 7 checks")

    Uninitialised state

    A flop without reset powers up x in simulation. Synthesis has no universal power-up value, and whether an initial value survives into gates varies by flow.

    Until the first reset, every decision made from that state is an x decision. Tests that skip reset check hardware that cannot exist yet.

    The init rule

    Give every state that must start known a reset or initial value that both simulation and gates honour; for intentionally unreset flops (pipelined datapaths, memories) apply reset before real vectors and show the result is X-tolerant.

    Common pitfall

    A test that passes with x forced to 0 in simulation proves the reset value, not the power-up value. The gates still wake in whatever state the silicon gives them.

    Interview

    Likely probe: name one optimistic and one pessimistic X each. Optimistic: x & 0 is 0 and if (x) takes else. Pessimistic: an x select falls to default while hardware takes a branch.

    Check yourself RTL computes y = x & 0 and the testbench is happy. What may the gates do differently?

    Nothing here: one leg is 0, so the gate agrees. The danger is the reverse case, where simulation keeps an x that hardware resolves.

    Check yourself A state register has no reset and the first test vector arrives immediately. What does simulation check?

    An x machine. Every branch from uninitialised state is an x decision, so the test checks decisions the gates never face after reset.

    Related topics

    • Previous: Blocking and non-blocking

    • Next: Case priority and wildcards

    • Reading netlists and reports

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    See also

    • Sensitivity Lists and Races
    • Directives, Widths, and Gate Simulation