A netlist and its reports answer three questions: what cells were used, how much area they take, and where the longest path runs. This topic reads each report line by line on small designs with checked counts.
Report | What it answers |
|---|---|
stat | How many cells of each type the design holds, and how many wires connect them. |
stat -liberty | How much area each cell type contributes, in library units of the teaching library. |
ltp | How many gates sit on the longest topological path through the design. |
write_verilog | A structural netlist that can be read back and recounted gate by gate. |
Lesson | What it covers |
|---|---|
Cell counts by type and wire counts on a checked three-gate example. | |
Area in library units, hand-added totals, and what area cannot tell you. | |
Flattening, fanout arithmetic, generated names, and constant pins. | |
Longest topological path with ltp, plus a write, read-back and recount loop. |
It tells cell area by type in library units. It tells nothing about wire area or placement, which appear only later in the flow.