Logic synthesis turns RTL, constraints, and a cell library into a gate-level netlist plus reports. The same RTL gives different netlists under different constraints.
Term | Meaning |
|---|---|
RTL | The register-transfer description of what the design does each clock cycle. |
Constraints | Timing and electrical targets the implementation must meet, such as the clock period. |
Cell library | The available gates and flops with their area and timing, here the teaching library course.lib. |
Netlist | The chosen cells and their wiring: the implementation carried forward. |
Reports | Cell counts, area by cell type, and timing figures describing the chosen netlist. |
Lesson | What it covers |
|---|---|
Inputs, outputs, flow position, and area in library units. | |
Elaboration, generic optimisation, mapping, post-map work, and reporting. | |
One RTL under two targets, with illustrative constraints and an area model. | |
A real Yosys flow on one design, with assertions pinning robust mapped facts. | |
Why commercial tools match these concepts, and what this course uses. |
Inputs: RTL, constraints, and the cell library. Outputs: the gate-level netlist and its reports.