Synthesis reads three things: the RTL, the constraints, and the cell library. It writes two things: the gate-level netlist and the reports that describe it.
Side | Item | Role |
|---|---|---|
In | RTL | Behaviour to implement; function must be preserved. |
In | Constraints | Targets to meet; these steer every choice. |
In | Cell library | Cells to build from; nothing else may appear. |
Out | Gate-level netlist | Chosen cells and wiring implementing the RTL. |
Out | Reports | Counts, area, and timing of the chosen netlist. |
Change any input and the output may change. That is expected behaviour, not tool noise.
Synthesis sits between design entry and the physical flow. RTL enters from above, and the netlist leaves toward placement with its reports.
Area is reported in library units of the teaching library course.lib. One unit is not a process dimension; it only compares cells inside this course.
Cell | Area (library units) |
|---|---|
INV | 1 |
NAND2, NOR2 | 2 |
AND2, OR2 | 3 |
MUX2 | 5 |
DFF | 8 |
The example below adds one small count by hand. The Python lesson later checks the same sum in code.
EXAMPLE counts with course.lib areas, in library units
counts: 5 NAND2, 2 INV, 1 DFF
area = 5 x 2 + 2 x 1 + 1 x 8 = 10 + 2 + 8 = 20 library units
shares: NAND2 10 / 20 = 50%, INV 2 / 20 = 10%, DFF 8 / 20 = 40%
50 + 10 + 40 = 100No. Constraints steer the choice of cells and structure, so a different target legitimately gives a different netlist for the same RTL.
20 library units: 5 x 2 + 2 x 1 + 1 x 8. The units are library units of the teaching library course.lib.