Constraints steer the tool

Constraints tell the tool what counts as good enough: the clock target and the electrical limits. The tool then picks cells and structures that meet them.

One RTL, two targets

The same RTL under a relaxed clock target leaves a small slow cover acceptable. The block below is an illustrative sketch, not tool output.

illustrative SDC sketch, not tool output
create_clock -period 10.0 [get_ports clk]
set_input_delay 2.0 -clock clk [all_inputs]
set_output_delay 2.0 -clock clk [all_outputs]

A tighter target may push the tool toward faster cells or a more parallel structure. The block below sketches that tighter target, again illustrative.

illustrative SDC sketch, not tool output
create_clock -period 5.0 [get_ports clk]
set_input_delay 1.0 -clock clk [all_inputs]
set_output_delay 1.0 -clock clk [all_outputs]

The two runs implement the same function with different cells. Which cover wins varies by tool and library, so no transform always helps.

A small area model

The program below prices a netlist from cell counts at course.lib areas. Its three self-checks repeat the hand arithmetic style of this topic.

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import sys

AREA = {"NAND2": 2, "INV": 1, "DFF": 8}

def design_area(counts):
    total = 0
    for cell in counts:
        total += counts[cell] * AREA[cell]
    return total

checks = [
    (design_area({"NAND2": 5, "INV": 2, "DFF": 1}), 20),
    (design_area({"NAND2": 1}), 2),
    (design_area({"DFF": 2, "INV": 3}), 19),
]

for i in range(len(checks)):
    got, want = checks[i]
    if got != want:
        print("FAIL: check " + str(i + 1) + " got " + str(got) + " want " + str(want))
        sys.exit(1)

print("PASS: area model matches hand arithmetic on 3 checks")

A tighter target may accept a larger area for more speed. The model prices that trade by counting cells, never by guessing.

Common mistakes

Related topics

• A small design through Yosys

• SDC for Synthesis

• Area Power Timing Tradeoffs