This course uses a five-stage model of synthesis. Real tools cover the same concepts but may iterate, merge, or reorder steps, and they differ in commands and options.
Stage | What it does |
|---|---|
1. Elaboration | Builds a generic hardware graph from the RTL: operators, muxes, flops, and hierarchy. |
2. Generic optimisation | Simplifies that graph with no library: constant folding, cleanup, and logic reduction. |
3. Technology mapping | Covers the graph with real library cells, choosing cells for the constraints. |
4. Post-map optimisation | Touches up the mapped netlist: sizing, buffering, and small local rewrites. |
5. Reporting | Writes the netlist plus counts, area, and timing for review. |
Elaboration turns RTL operators into generic gates, and hierarchy plus processes into flat logic and flops. In Yosys these are the hierarchy and proc steps (this course also flattens the small examples so counts read flat).
Generic optimisation then shrinks the graph before any library cell is chosen. In Yosys this is the opt family of passes.
Technology mapping covers the simplified graph with library cells. In Yosys this is techmap followed by abc against the course library.
Post-map optimisation adjusts the mapped result, and reporting writes the netlist with its counts and area. In Yosys reporting is stat against the same library.
Optimisation never changes function, only cost and shape. Equivalence between RTL and netlist is covered in its own topic.
In stage 3, technology mapping. Stages 1 and 2 work only with generic gates.
No. Generic gates are not library cells, so only the post-map stat report gives library area.