A # delay advances simulation time only. It has no gate-level meaning, so it never appears in the netlist.
The listing below is not run: it uses delays and display calls, neither of which synthesizes.
// not-run: uses delays and display calls, neither synthesizes
module delay_demo (
input wire clk,
output reg q
);
initial begin
q = 1'b0;
end
always @(posedge clk) begin
#10 q <= ~q;
$display("toggled");
end
endmoduleinitial blocks, file access, and $display steer simulation. They describe the testbench rather than the chip, so the tool leaves them out of the netlist.
Some flows read initial values as power-up states. That meaning varies between tools, so keep initial blocks in testbenches.
real numbers and strings have no bit-level hardware mapping. Testbenches and models may use them freely, but RTL may not.
Construct | Synthesizable | Use instead |
|---|---|---|
| Yes | Fixed-width state and data |
| Yes, at elaboration | Constant loop bounds |
| No | Scaled integers and vectors |
| No | Clocked sequencing |
| Testbench only | Reset logic |
#10 delay sits in RTL. What hardware does it become?None. Delays advance simulation time only and never reach the netlist.
initial block sets a counter at time zero. Why might the chip disagree?The block is testbench code. Unless the flow documents power-up values, nothing on the chip performs that step, so use reset logic instead.