An always block triggered on a clock edge infers one flip-flop per bit. Branches inside it become enable or data muxes, never latches.
The script below reads one flop and pins exactly one $dff with no $dlatch. Areas below are teaching-library units, with DFF at 8 and DFFR at 10.
read_verilog <<EOV
module dff_top (
input wire clk,
input wire d,
output reg q
);
always @(posedge clk) begin
q <= d;
end
endmodule
EOV
hierarchy -check -top dff_top
proc
select -assert-count 1 t:$dff
select -assert-none t:$dlatch
log PASS: clocked block infers one flop with no latch8-bit register from the teaching library
DFF area is 8 units, DFFR area is 10 units
no reset: 8 x 8 = 64 units
with reset: 8 x 10 = 80 units
reset cost = 80 - 64 = 16 unitsAn output driven to high impedance infers a tri-state driver. Such drivers map cleanly to chip pins and shared buses.
Inside the core most flows convert them to multiplexers instead. The exact handling varies between tools, so keep tri-states at the boundary.
A for loop with bounds fixed at elaboration unrolls into repeated hardware. Eight iterations build eight copies, not one reused unit.
The program below replays the worked arithmetic of this topic. Its six self-checks repeat the hand totals for select depth and register area.
import sys
MUX2_AREA = 5
DFF_AREA = 8
DFFR_AREA = 10
def tree_cells(n):
return n - 1
def tree_depth(n):
d = 0
p = 1
while p < n:
p = p * 2
d = d + 1
return d
def chain_depth(n):
return n - 1
def mux_area(n):
return tree_cells(n) * MUX2_AREA
def reg_area(bits, with_reset):
cell = DFFR_AREA if with_reset else DFF_AREA
return bits * cell
checks = [
(tree_cells(8), 7),
(tree_depth(8), 3),
(chain_depth(8), 7),
(mux_area(8), 35),
(reg_area(8, False), 64),
(reg_area(8, True), 80),
]
for i in range(len(checks)):
got, want = checks[i]
if got != want:
print("FAIL: check " + str(i + 1) + " got " + str(got) + " want " + str(want))
sys.exit(1)
print("PASS: depth and area arithmetic agrees on 6 checks")if without an else skips the register update on one branch. Latch or flop?Flop with an enable path. Clocked blocks infer storage with enables, never latches.
80 units. The reset term costs 16 units over the 64 of the plain register.