Combinational blocks

An assign statement and a combinational always block describe pure logic. A synthesis tool builds gates and multiplexers from them, with no storage.

A combinational block names its inputs implicitly with always @*. Simulation and synthesis agree when every path through the block assigns every output.

Complete assignment

Complete assignment means each output gets a value on every path. An if with an else, and a case covering every value with a default, both qualify.

What the tool builds

The script below reads one 2:1 multiplexer and runs the generic front end. It pins exactly one $mux with no $dlatch and no $dff.

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read_verilog <<EOV
module mux_top (
  input wire a,
  input wire b,
  input wire sel,
  output reg y
);
  always @* begin
    if (sel)
      y = b;
    else
      y = a;
  end
endmodule
EOV
hierarchy -check -top mux_top
proc
select -assert-count 1 t:$mux
select -assert-none t:$dlatch
select -assert-none t:$dff
log PASS: complete branch infers one mux with no latch and no flop

Common mistakes

Related topics

• Priority Chains versus Parallel Selects

• Reading Netlists and Reports

• Muxes, Decoders and Encoders