stat reports how many cells of each type the design holds. It also reports the wire count, which covers ports and internal nets together.
Run it on the generic netlist to see the tool-neutral structure, and again after mapping to see library cells. The block below is an illustrative layout, numbers invented for this lesson.
illustrative layout, numbers invented for this lesson (an example slice, never tool output):
cells: NAND2 12, NOR2 4, INV 6, DFF 8
total cells = 12 + 4 + 6 + 8 = 30
wires = 41 (stated with the layout)Three nouns carry every report. A cell is one gate or flop instance, a wire is one net, and a pin is one connection point on a cell.
Term | Meaning |
|---|---|
Cell | One instance of a gate or flop, counted under its type. |
Wire (net) | One named connection: a port or an internal net. |
Pin | One terminal of a cell, such as an input or an output. |
Port | A wire that crosses the module boundary. |
The design below ANDs two pairs and ORs the results. Its script pins every number the lesson quotes: two $and cells, one $or cell and three gates in total.
read_verilog <<EOV
module top(input a, b, c, d, output y);
wire n1, n2;
assign n1 = a & b;
assign n2 = c & d;
assign y = n1 | n2;
endmodule
EOV
hierarchy -check -top top
select -assert-count 2 t:$and
select -assert-count 1 t:$or
select -assert-count 3 t:$and t:$or %u
stat
log PASS: three gates elaborate as writtenThree gates implement the function: two ANDs feeding one OR.
Three gates: two ANDs feeding one OR. The union selection pins that total in one assertion.
The total hides which cells dominate. Without the by-type split, there is nothing to resize or restructure.