A standard-cell library lists every cell a mapper may use, with its function, area, pin capacitance, timing arcs, and delay tables. The mapper trades these entries against each other on every path.
Entry | What it tells the tool |
|---|---|
Function | The Boolean function of each output in terms of the inputs. |
Area | The cost of using the cell once, in library area units. |
Pin capacitance | The load each input pin adds to its driver. |
Timing arc | One input-to-output path with a sense and a delay table. |
Delay table | Delay and output slew indexed by input slew and output load. |
Flop constraints | Setup and hold limits plus clock-to-output delay. |
Power data | Leakage and switching energy per cell and per arc. |
Lesson | What it covers |
|---|---|
Function, area, capacitance, arcs, tables, and power entries. | |
The course library cell by cell with an abridged excerpt. | |
Two-index delay tables with a runnable interpolation. | |
Setup and hold, drive strength, Vt flavours, and power. | |
A Yosys run that maps two gates to library cells. |
Input slew and output load. The table entry at that point gives the delay.