Reading the Teaching Library · synthesis

Part 2 · Logic Optimisation and Mapping · Intermediate

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The teaching library

The course library is a small fictional library called course, kept in course.lib. It holds fifteen cells with fixed EXAMPLE areas in library units.

A second library, nand_only.lib, holds only INV, BUF, and NAND2. Comparing mappings across the two shows what cell choice costs.

Cell	Function	Area
INV	`!A`	1
BUF	`A`	2
NAND2	`!(A*B)`	2
NOR2	`!(A+B)`	2
AND2	`A*B`	3
OR2	`A+B`	3
NAND3	`!(ABC)`	3
NOR3	`!(A+B+C)`	3
XOR2	`A^B`	5
XNOR2	`!(A^B)`	5
AOI21	`!((A*B)+C)`	3
OAI21	`!((A+B)*C)`	3
MUX2	`(SB)+(!SA)`	5
DFF	Rising-edge flop	8
DFFR	Rising-edge flop with reset	10

Abridged excerpt

The text block below is an ABRIDGED excerpt from course.lib, with tables shortened to their shape and corner values. It is not the full file.

Diagram

ABRIDGED excerpt from course.lib (fictional teaching library, tables shortened)
library(course) {
  delay_model : table_lookup;
  time_unit : "1ns";
  lu_table_template(dt) {
    variable_1 : input_net_transition;
    variable_2 : total_output_net_capacitance;
    index_1("0.01, 0.1");
    index_2("0.01, 0.1");
  }
  cell(INV) {
    area : 1;
    pin(A) { direction : input; capacitance : 0.01; }
    pin(Y) {
      direction : output; function : "!A"; max_capacitance : 1.0;
      timing() { related_pin : "A"; timing_sense : negative_unate;
        cell_rise(dt) { index_1("0.01, 0.1"); index_2("0.01, 0.1");
          values("0.05, ...", "0.07, ..."); } }
    }
  }
  cell(NAND2) {
    area : 2;
    pin(A) { direction : input; capacitance : 0.01; }
    pin(B) { direction : input; capacitance : 0.01; }
    pin(Y) {
      direction : output; function : "!(A*B)"; max_capacitance : 1.0;
      timing() { related_pin : "A"; timing_sense : negative_unate;
        cell_rise(dt) { index_1("0.01, 0.1"); index_2("0.01, 0.1");
          values("0.08, ...", "0.10, ..."); } }
    }
  }
}

Reading one cell

Read a cell top to bottom: area first, then pin functions and capacitances, then one timing group per arc. Each delay table repeats the two index axes from the template.

A second timing group with the other input pin holds the matching table. Flop cells replace output arcs with constraint and clock-to-output groups, covered in a later lesson.

Check yourself What are the INV and NAND2 areas, and what does each input pin load its driver with?

INV is 1 unit and NAND2 is 2 units. Each input pin adds 0.01 load units.

Check yourself Why is the excerpt unsafe for delay lookup?

Its tables are shortened to corner values. Only full tables give exact entries for interpolation.

Related topics

Up nextDelay Tables and Interpolation

Practice this lesson Report an error

The teaching library

The course library is a small fictional library called course, kept in course.lib. It holds fifteen cells with fixed EXAMPLE areas in library units.

A second library, nand_only.lib, holds only INV, BUF, and NAND2. Comparing mappings across the two shows what cell choice costs.

Cell	Function	Area
INV	`!A`	1
BUF	`A`	2
NAND2	`!(A*B)`	2
NOR2	`!(A+B)`	2
AND2	`A*B`	3
OR2	`A+B`	3
NAND3	`!(ABC)`	3
NOR3	`!(A+B+C)`	3
XOR2	`A^B`	5
XNOR2	`!(A^B)`	5
AOI21	`!((A*B)+C)`	3
OAI21	`!((A+B)*C)`	3
MUX2	`(SB)+(!SA)`	5
DFF	Rising-edge flop	8
DFFR	Rising-edge flop with reset	10

Abridged excerpt

The text block below is an ABRIDGED excerpt from course.lib, with tables shortened to their shape and corner values. It is not the full file.

Diagram

ABRIDGED excerpt from course.lib (fictional teaching library, tables shortened)
library(course) {
  delay_model : table_lookup;
  time_unit : "1ns";
  lu_table_template(dt) {
    variable_1 : input_net_transition;
    variable_2 : total_output_net_capacitance;
    index_1("0.01, 0.1");
    index_2("0.01, 0.1");
  }
  cell(INV) {
    area : 1;
    pin(A) { direction : input; capacitance : 0.01; }
    pin(Y) {
      direction : output; function : "!A"; max_capacitance : 1.0;
      timing() { related_pin : "A"; timing_sense : negative_unate;
        cell_rise(dt) { index_1("0.01, 0.1"); index_2("0.01, 0.1");
          values("0.05, ...", "0.07, ..."); } }
    }
  }
  cell(NAND2) {
    area : 2;
    pin(A) { direction : input; capacitance : 0.01; }
    pin(B) { direction : input; capacitance : 0.01; }
    pin(Y) {
      direction : output; function : "!(A*B)"; max_capacitance : 1.0;
      timing() { related_pin : "A"; timing_sense : negative_unate;
        cell_rise(dt) { index_1("0.01, 0.1"); index_2("0.01, 0.1");
          values("0.08, ...", "0.10, ..."); } }
    }
  }
}

Reading one cell

Read a cell top to bottom: area first, then pin functions and capacitances, then one timing group per arc. Each delay table repeats the two index axes from the template.

A second timing group with the other input pin holds the matching table. Flop cells replace output arcs with constraint and clock-to-output groups, covered in a later lesson.

Check yourself What are the INV and NAND2 areas, and what does each input pin load its driver with?

INV is 1 unit and NAND2 is 2 units. Each input pin adds 0.01 load units.

Check yourself Why is the excerpt unsafe for delay lookup?

Its tables are shortened to corner values. Only full tables give exact entries for interpolation.