Each cell entry starts with its Boolean function and its area. The function tells the mapper what the cell computes, and the area tells it what that costs.
Every input pin adds a capacitance entry. That number is the load seen by the driving cell.
Entry | Example from the teaching library |
|---|---|
Function | NAND2 output is |
Area | NAND2 costs 2 units; INV costs 1 unit. |
Pin capacitance | Each input pin presents 0.01 load units. |
Timing arc | Each input has a rise and a fall arc to the output. |
Delay table | Each arc carries tables indexed by slew and load. |
Area is quoted in library units of the teaching library, never in real process units. The mapper adds cell areas to score one mapping against another.
Pin capacitance sets fanout load: one driver sees the sum of its driven pins. Larger loads index slower points in the delay tables.
EXAMPLE areas from the teaching library (library units): NAND2 = 2, INV = 1
small block: 2 NAND2 cells and 1 INV cell
area = 2 x 2 + 1 x 1 = 4 + 1 = 5 library unitsA timing arc links one input pin to one output pin with a timing sense. Combinational arcs carry delay tables; flop entries carry setup, hold, and clock-to-output data.
Power data rides alongside: leakage per cell and switching energy per arc. The teaching library omits power tables, so power numbers here are EXAMPLE parameters stated per lesson.
Five library units: 2 x 2 + 1 x 1 = 5.
Three times 0.01, which is 0.03 load units, before any wire load.