A flop entry replaces output arcs with three groups: setup and hold limits on D against CLK, and clock-to-output delay. Each group carries its own two-index table.
The teaching DFF uses EXAMPLE setup values near 0.06 and hold values near 0.01. Clock to output sits near 0.18 EXAMPLE ns.
Entry | Corner values (EXAMPLE ns) |
|---|---|
Setup, rising | 0.05, 0.06 on the first row and 0.06, 0.07 on the second. |
Hold, rising | 0.0, 0.01 on the first row and 0.01, 0.02 on the second. |
Clock to Q | 0.15, 0.17 on the first row and 0.18, 0.21 on the second. |
EXAMPLE parameters: clock period = 1.0 ns, data arrival = 0.60 ns, setup = 0.06 ns
required = period - setup = 1.0 - 0.06 = 0.94 ns
slack = required - arrival = 0.94 - 0.60 = 0.34 nsDrive strength is the same function in a larger size: more drive at more area and power. The teaching library lists one size per function, so it offers no strength choice.
A Vt flavour is a process option that trades speed for leakage: low Vt is faster and leakier, high Vt is slower and tighter. The teaching library carries no Vt split, and real libraries vary in what they offer.
Choice | Faster side | Cheaper side |
|---|---|---|
Drive strength | A larger cell drives more load sooner. | A smaller cell costs less area and power. |
Vt flavour | Low Vt switches faster. | High Vt leaks less. |
Library power data has two parts: leakage per cell and switching energy per arc. Both move with the same choices as delay: size, Vt flavour, slew, and load.
The teaching library omits power tables. Power arithmetic below therefore uses stated EXAMPLE parameters, not library data.
EXAMPLE parameters (not library data): activity = 0.2, C = 10 fF, V = 1.0 V, f = 100 MHz
P = activity x C x V^2 x f
= 0.2 x 10e-15 F x (1.0 V)^2 x 100e6 Hz
= 0.2 x 10e-15 x 1.0 x 1e8 W
= 0.2 x 1e-6 W = 0.2 uWRequired is 0.94 ns. Slack is 0.94 - 0.60 = 0.34 ns.
0.2 uW: 0.2 x 10e-15 x 1.0 x 1e8 = 0.2e-6 W.