A behavioural 4-bit adder, s = a + b, is synthesised and then mapped twice with ABC: once to the full teaching library and once to a NAND-only variant. Areas below are library units of the fictional teaching library, never silicon figures.
Cell | Area | Cell | Area |
|---|---|---|---|
INV | 1 | XNOR2 | 5 |
BUF | 2 | AOI21 | 3 |
NAND2 | 2 | OAI21 | 3 |
NOR2 | 2 | MUX2 | 5 |
AND2 | 3 | DFF | 8 |
OR2 | 3 | DFFR | 10 |
NAND3 | 3 | ||
NOR3 | 3 | ||
XOR2 | 5 |
The restricted variant, nand_only.lib, holds only INV, BUF, and NAND2 at the same areas. Every other function must be built from those three.
The first block maps the adder to course.lib and proves the netlist holds no generic gates. The stat line reports the area for this exact course build: 52 area units.
read_verilog <<EOV
module adder4(input [3:0] a, b, output [4:0] s);
assign s = a + b;
endmodule
EOV
synth -top adder4
abc -liberty course.lib
stat -liberty course.lib
select -assert-none t:$and
select -assert-none t:$or
select -assert-none t:$xor
select -assert-none t:$xnor
select -assert-none t:$mux
select -assert-none t:$not
select -assert-none t:$_AND_
select -assert-none t:$_OR_
select -assert-none t:$_XOR_
select -assert-none t:$_XNOR_
select -assert-none t:$_MUX_
select -assert-none t:$_NOT_
select -assert-none t:$_NAND_
select -assert-none t:$_NOR_
check
log PASS: adder4 maps to course.lib cells with no generic gates leftThe second block maps the same adder to nand_only.lib and proves only INV, BUF, and NAND2 remain. The stat line reports 68 area units on the same build.
read_verilog <<EOV
module adder4(input [3:0] a, b, output [4:0] s);
assign s = a + b;
endmodule
EOV
synth -top adder4
abc -liberty nand_only.lib
stat -liberty nand_only.lib
select -assert-none t:$and
select -assert-none t:$or
select -assert-none t:$xor
select -assert-none t:$xnor
select -assert-none t:$mux
select -assert-none t:$not
select -assert-none t:$_AND_
select -assert-none t:$_OR_
select -assert-none t:$_XOR_
select -assert-none t:$_XNOR_
select -assert-none t:$_MUX_
select -assert-none t:$_NOT_
select -assert-none t:$_NAND_
select -assert-none t:$_NOR_
select -assert-none t:AND2
select -assert-none t:OR2
select -assert-none t:XOR2
select -assert-none t:XNOR2
select -assert-none t:NAND3
select -assert-none t:NOR3
select -assert-none t:AOI21
select -assert-none t:OAI21
select -assert-none t:MUX2
select -assert-none t:DFF
select -assert-none t:DFFR
select -assert-min 1 t:NAND2
check
log PASS: adder4 maps to INV BUF NAND2 only with no generic gates leftLibrary | Cells available | Area (area units) |
|---|---|---|
course.lib | 15 | 52 |
nand_only.lib | 3 | 68 |
this exact course build and library (example result, not a guarantee)
course.lib area = 52 area units
nand_only.lib area = 68 area units
difference = 68 - 52 = 16 area units
ratio = 68 / 52 = 1.3077, about 1.31xThe restricted cover costs more because sums need XOR behaviour. The full library offers it in one cell; the restricted library builds it from several NAND2 cells, and the extra gates outweigh the saving per cell.
Sums need XOR behaviour. The full library offers it in one cell, while the restricted library builds it from several NAND2 cells.
That the named generic gate kind is gone from the mapped netlist. Together they prove the mapping reached library cells.