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Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
    • Boolean Optimisation
    • Technology Mapping
      • Covering a Network with Cells
      • Cuts and Matching
      • Area Against Delay
      • Inverters and Banned Cells
      • Mapping in Yosys
    • Cell Libraries and Liberty
    • Structuring and Buffering
  • Constraints and Timing15
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
  • Area, Power and Test14
  • Verification, ECO and Handoff15
  • Flows and Debugging15
  • Interview and Judgment11
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‹Technology Mapping
  1. Topics
  2. Logic Synthesis
  3. Logic Optimisation and Mapping
  4. Technology Mapping
  5. Area Against Delay

Part 2 · Logic Optimisation and Mapping · Intermediate

Area Against Delay

Area cost, arrival times, and why the cheapest cell is not always chosen.

On this page

    Two objectives

    Area mapping minimises the sum of cell areas. Delay mapping minimises arrival times against the required times, path by path.

    Mode

    Cost

    Decision

    Area

    Sum of cell areas

    Cheapest cover that implements the function.

    Delay

    Worst arrival against required time

    Fastest cover on each failing path, cheapest elsewhere.

    The two modes disagree when the cheapest cover is too slow for the required time. The next section works one such case.

    A worked choice

    Take f = NOT ((a AND b) OR c) again, with EXAMPLE delays in delay units. Cover C is cheapest; cover A answers whether it is fastest.

    Cover

    Cells

    Area

    Delay

    Slack at required 5

    C

    AOI21

    3

    6

    -1, fails

    A

    AND2 + NOR2

    5

    5

    0, meets

    B

    NAND2 + INV + NAND2 + INV

    6

    5

    0, meets

    Diagram
    f = NOT ((a AND b) OR c); EXAMPLE delays in delay units: INV 1, NAND2 2, NOR2 2, AND2 3, AOI21 6
    cover C: area = 3; arrival = 6; slack = 5 - 6 = -1 (fails)
    cover A: area = 3 + 2 = 5; arrival = 3 + 2 = 5; slack = 5 - 5 = 0 (meets)
    cover B: area = 2 + 1 + 2 + 1 = 6; arrival = 2 + 2 + 1 = 5; slack = 5 - 5 = 0 (meets)
    area choice = cover C; delay choice at required 5 = cover A

    Slack is required time minus arrival time. Area mode picks C; delay mode at required 5 pays two extra area units for A and meets timing.

    Common mistakes

    Common pitfall

    Trimming area on a path that already fails delay buys a small saving at the price of a violation. Shrink logic off the critical path first.

    Interview

    Likely question: the smallest cell fits, so why did the tool skip it?

    • The path needed the faster cover: slack decides, not area alone.

    • The small cell could not drive the load within the slew limit.

    • The cell was banned by a dont_use entry, covered in the next lesson.

    Check yourself At a required time of 6, which covers meet timing and which one does area mode pick?

    All three meet: C with slack 0, A and B with slack 1. Area mode picks C at area 3.

    Check yourself Load doubles on the output of cover A. What may the mapper do, and what does it cost?

    It may swap in a higher-drive variant of the same function where the library provides one. The swap costs extra area for the same logic.

    Related topics

    • Cuts and Matching

    • Inverters and Banned Cells

    • See also: Area, Power and Timing Tradeoffs

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    See also

    • Covering a Network with Cells
    • Mapping in Yosys