An inverter at a gate input is a bubble. De Morgan pushes bubbles through gates: NOT (a AND b) is (NOT a) OR (NOT b), and the dual holds for OR.
The mapper slides bubbles until they merge: an inverter over an AND becomes a NAND2, and a leftover pair folds into an AOI or OAI cell.
y = NOT ((NOT a) AND (NOT b)); areas in teaching-library area units
before: INV (1) + INV (1) + NAND2 (2) = 4
De Morgan: y = a OR b
after: OR2 (3) = 3
saving = 4 - 3 = 1 area unitFor each output the mapper can build the function or its complement plus an inverter. It keeps whichever cover is cheaper.
Function | Direct | Complement plus inverter | Cheaper |
|---|---|---|---|
a XOR b | XOR2 (5) | XNOR2 (5) + INV (1) = 6 | XOR2 |
NOT (a XOR b) | XNOR2 (5) | XOR2 (5) + INV (1) = 6 | Direct |
Libraries mark some cells dont_use, and the mapper must skip them even when they match. A ban can come from several causes.
Cause | Effect on the cover |
|---|---|
Cell not characterised for this corner | Mapper routes around it. |
Cell kept only for legacy netlists | New logic never uses it. |
Footprint the block cannot route | Local covers grow larger. |
Every ban shrinks the choice set, so area or delay can slip. Recheck both after each ban.
An OR2 implements y directly at 3 area units. The saving is 1 area unit.
The mapper must skip it and cover the cone another way. If no cover remains, the library setup needs fixing, not the rule.