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Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
    • Boolean Optimisation
    • Technology Mapping
      • Covering a Network with Cells
      • Cuts and Matching
      • Area Against Delay
      • Inverters and Banned Cells
      • Mapping in Yosys
    • Cell Libraries and Liberty
    • Structuring and Buffering
  • Constraints and Timing15
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
  • Area, Power and Test14
  • Verification, ECO and Handoff15
  • Flows and Debugging15
  • Interview and Judgment11
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‹Technology Mapping
  1. Topics
  2. Logic Synthesis
  3. Logic Optimisation and Mapping
  4. Technology Mapping
  5. Covering a Network with Cells

Part 2 · Logic Optimisation and Mapping · Intermediate

Covering a Network with Cells

Subject graphs, library patterns, and covers: what technology mapping chooses.

On this page

    The subject graph

    Mapping starts from a Boolean network of simple gates such as AND, OR, and inverters. Call it the subject graph: nodes are gates and edges are wires.

    The library offers cells such as NAND2, AOI21, and MUX2. Each cell is a pattern: a small gate shape with an area cost.

    Patterns and covers

    A cover assigns every subject node to exactly one cell. The cover is valid only when each cell input connects to a primary input or to another cell output.

    • Every node belongs to exactly one cell, including inverters.

    • A cell matches only where its function fits the gates it covers.

    • The cover cost is the sum of its cell areas in library area units.

    A first cover

    Take f = NOT ((a AND b) OR c) with course library areas. Three covers compete, and the calc block adds each one.

    Cover

    Cells

    Area (area units)

    A

    AND2 + NOR2

    5

    B

    NAND2 + INV + NAND2 + INV

    6

    C

    AOI21

    3

    Diagram
    f = NOT ((a AND b) OR c); areas in teaching-library area units
    cover A = AND2 (3) + NOR2 (2) = 5
    cover B = NAND2 (2) + INV (1) + NAND2 (2) + INV (1) = 6
    cover C = AOI21 (3) = 3
    cheapest of the three = cover C at 3 area units

    Cover C wins because one AOI21 cell absorbs the AND, the OR, and the output inversion. Fewer, better-fitting cells beat more generic ones.

    Cover B really implements f: with n1 = NAND2(a, b), nc = INV(c), m = NAND2(n1, nc), and y = INV(m), the output column matches f on every input row.

    a b c

    f

    cover B y

    000

    1

    1

    001

    0

    0

    010

    1

    1

    011

    0

    0

    100

    1

    1

    101

    0

    0

    110

    0

    0

    111

    0

    0

    Common mistakes

    Common pitfall

    Forgetting the inverters: a cover must place every node, bubbles included. An unmapped inverter is unmapped logic, not free wiring.

    Interview

    Likely probes: subject, pattern, and cover.

    • The subject is the gate network; a pattern is one cell shape.

    • A cover places every node exactly once; its cost is summed areas.

    • AOI and MUX cells exist to absorb whole cones at once.

    Check yourself For f above, which cover is cheapest and what is its area?

    Cover C, a single AOI21 at 3 area units.

    Check yourself A cover leaves one inverter unassigned. Is the cover valid?

    No. Every node needs a cell, including inverters. The unassigned node is logic the netlist does not implement.

    Related topics

    • Cuts and Matching

    • Boolean Optimisation

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    See also

    • Area Against Delay
    • Inverters and Banned Cells
    • Mapping in Yosys