Flows honor hidden-region directives that mark test-only code for simulation. The gates never contain that region, by design.
The sketch below is illustrative and not runnable: directive spellings vary by flow, so the wording here is generic.
illustrative hidden-region sketch (not runnable; spelling varies by flow)
design logic stays outside the hidden region and synthesizes as usual
a monitor inside the hidden region prints in simulation and is absent from gates
a test that only passes because of hidden-region behaviour proves nothing about gatesKeep every behaviour the gates must show outside hidden regions. A passing test that depends on hidden code is testing the testbench.
Unsized literals default to 32-bit signed values, and assignments keep only the low bits that fit. A select sized for eight inputs cannot address a ninth.
Trap | Example | Rule |
|---|---|---|
Truncation |
| Size every literal to its target |
Select width | Five inputs need 3 select bits, leaving 3 unused codes | Size selects from the count and define the extras |
Sign extension | Unsized | Size and sign every constant in an expression |
The program below checks the truncation counts and the select widths. Its seven self-checks pin every number the lesson quotes.
import sys
bad = 0
def check(name, got, want):
global bad
if got != want:
print("FAIL: " + name + " got " + str(got) + " want " + str(want))
bad = bad + 1
def trunc4(v):
return v & 15
check("hex-AB-to-4b", trunc4(171), 11)
check("fits-kept", trunc4(9), 9)
changed = 0
for v in range(256):
if trunc4(v) != v:
changed = changed + 1
check("changed-of-256", changed, 240)
check("kept-of-256", 256 - changed, 16)
def sel_width(n):
return (n - 1).bit_length()
check("selw-5", sel_width(5), 3)
check("selw-8", sel_width(8), 3)
check("selw-9", sel_width(9), 4)
if bad != 0:
sys.exit(1)
print("PASS: truncation counts and select widths agree on 7 checks")Zero-delay gate simulation evaluates each gate once per pass with no durations, so glitches never appear. Timed simulation annotates EXAMPLE delays at concept level, so pulses and ordering become visible.
EXAMPLE delays (classroom parameters, not real data): clk-to-q 2, inv 1, nand2 2, mux2 3, setup 1, period 20
path: q -> inv -> nand2 -> mux2 -> D
arrival = 2 + 1 + 2 + 3 = 8
required = 20 - 1 = 19
slack = 19 - 8 = 11
the nand2 leg settles at 2 + 1 + 2 = 5, the mux output at 8
zero-delay simulation reports the settled D after one pass with no intermediate pulse
timed simulation reports the leg at 5 before the output at 8Run the failing RTL vector against the gate netlist twice: once with zero delay for function, once with annotated delays for timing. Mismatches that survive both are logic bugs.
Ones that appear only with delays are timing or constraint issues. That split decides whether the fix is in the RTL or in the timing setup.
0xAB lands in a 4-bit register. What arrives, and how many of the 256 byte values change this way?Low nibble B, which is 11. Values 16 to 255 change, which is 240 of 256; only 0 to 15 survive.
11. Required minus arrival is 19 minus 8, using the stated EXAMPLE delays.