A blocking assignment (=) updates the variable at once, so later lines in the same block see the new value. Combinational code uses it because each line is a wire continuing to the next.
In simulation, chaining three stages with = in one block collapses them. The input runs through every stage in the same evaluation.
Synthesis infers registers from the clocked structure, not from = against <=. The mismatch is that blocking assignments in a clocked block simulate as one collapsed stage while the inferred registers shift.
A non-blocking assignment (<=) samples the right-hand side now and applies it at the clock edge. Every register in the block therefore samples the pre-edge values together.
In simulation, the same three stages with <= form a real pipeline. Each stage hands its old value forward once per clock.
A three-stage register takes din = 1, 0, 1, 1 over cycles 1 to 4 from reset 0, 0, 0. The calc block traces both simulation behaviours exactly.
3-stage shift, din sequence 1, 0, 1, 1, reset q1 = q2 = q3 = 0
nonblocking (<=): each stage takes the pre-edge value
cycle 1: q1 = 1, q2 = 0, q3 = 0
cycle 2: q1 = 0, q2 = 1, q3 = 0
cycle 3: q1 = 1, q2 = 0, q3 = 1
cycle 4: q1 = 1, q2 = 1, q3 = 0
blocking (=) in one block: each line sees the new value above it
cycle 1: q1 = 1, q2 = 1, q3 = 1 (din jumps through all three stages at once)Style | Update | Use for | Breaks when |
|---|---|---|---|
Blocking `=` | Immediate, in order | Combinational blocks | Used for clocked state: simulates as one collapsed stage while inferred registers shift |
Non-blocking `<=` | Sampled now, applied at the edge | Clocked blocks | Used for combinational logic: simulates as deferred, staged updates and can disagree with the combinational gates; use |
Reading after a blocking write sees the new value, while reading after a non-blocking write sees the old one. Mixing both styles on one variable makes simulation order visible in the result.
q1 = din; q2 = q1; q3 = q2; with blocking assignments. How many clocks does din take to reach q3?None in simulation. Every line sees the update above it, so the trace shows 1, 1, 1 in cycle 1, while the inferred registers still shift one stage per clock.
<= and din is 1 only in cycle 1. When does q3 first read 1?Cycle 3. Each edge shifts one stage, so q3 reads 0, 0, 1 across cycles 1 to 3.