Synthesis runs before placement, so it cannot know wire lengths. Net delays at this stage are estimates, and their accuracy varies with the design and the flow.
Later stages replace estimates with extracted values. A path that meets timing on estimates can still fail after layout, and the reverse holds too.
Wire model | What it assumes | Risk |
|---|---|---|
Ideal wires | Net delay is zero; only cells count. | Optimistic: hides net-heavy paths. |
Wire-load estimate | Net delay grows with fanout or block size. | Blunt: over- and under-estimates across the block. |
Extracted (after layout) | Real lengths and coupling from the placed design. | Accurate, but unavailable during synthesis. |
Ideal-wire mode sets every net delay to zero. It suits early area or structure experiments, never timing closure.
A wire-load estimate assigns each net a delay from its fanout or the block size. It restores the missing net term crudely, so paths with heavy nets look worse than ideal wires suggest.
Take the EXAMPLE 0.54 ns of cell delay from the previous lesson with required time 1.00 ns. Ideal wires give arrival 0.54 ns; a wire-load estimate adds 0.15 ns of nets.
EXAMPLE parameters (not real library values): cells 0.54 ns, required 1.00 ns
ideal-wire arrival = 0.54 + 0.00 = 0.54 ns
ideal-wire slack = 1.00 - 0.54 = +0.46 ns
wire-load arrival = 0.54 + 0.15 = 0.69 ns
wire-load slack = 1.00 - 0.69 = +0.31 ns
the estimate removes 0.15 ns of apparent margin on the same cellsIdeal-wire slack is +0.46 ns; wire-load slack is +0.31 ns. The estimate costs 0.15 ns of margin.
Ideal wires drop the whole net term. A net-heavy path is exactly where the dropped term dominates.