Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
  • Constraints and Timing15
    • SDC for Synthesis
    • Delay Models and Slack
      • Arrival, Required Time and Slack
      • Setup, Hold and Clock-to-Q
      • Cell Delay Models
      • Wire Delay at Synthesis Time
      • A Static Timing Calculator
    • Timing-Driven Synthesis
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
  • Area, Power and Test14
  • Verification, ECO and Handoff15
  • Flows and Debugging15
  • Interview and Judgment11
Loading lesson

‹Delay Models and Slack
  1. Topics
  2. Logic Synthesis
  3. Constraints and Timing
  4. Delay Models and Slack
  5. Arrival, Required Time and Slack

Part 3 · Constraints and Timing · Intermediate

Arrival, Required Time and Slack

Arrival, required time and slack with a worked EXAMPLE in nanoseconds.

On this page

    Arrival and required time

    Arrival time is when a transition reaches a node, summed from the launching flop along the path. It adds the clock-to-Q delay to every cell and net delay on the way.

    Required time is the deadline at that node, set by the capturing clock edge minus margins. For a setup check with zero skew it is the clock period minus the setup time.

    Slack sign

    Meaning

    What follows

    Positive

    The signal arrives before it is needed.

    Margin exists; the path meets timing.

    Zero

    Arrival exactly meets the deadline.

    Met, with no margin for variation.

    Negative

    The signal arrives after it is needed.

    The path fails; its magnitude is the violation.

    Slack and the critical path

    Slack is required time minus arrival time, in nanoseconds. Each endpoint reports its worst slack, and the design reports the worst over all endpoints.

    The critical path is the path with the smallest slack. It limits the clock speed, so the tool spends its effort there first.

    A worked setup check

    Take an EXAMPLE 4.00 ns clock, a launch clock-to-Q of 0.30 ns, and 2.60 ns of combinational delay. The capturing flop needs 0.40 ns of setup.

    Diagram
    EXAMPLE parameters (not real library values): period 4.00 ns, clock-to-Q 0.30 ns, combo 2.60 ns, setup 0.40 ns
    arrival  = 0.30 + 2.60 = 2.90 ns
    required = 4.00 - 0.40 = 3.60 ns
    slack    = 3.60 - 2.90 = +0.70 ns -> path P1 meets timing
    a second path P2 arrives at 3.90 ns against the same required time
    slack P2 = 3.60 - 3.90 = -0.30 ns -> P2 violates and is the critical path

    Common mistakes

    Common pitfall

    Slack is required minus arrival, not the reverse. Reversing the subtraction turns a 0.30 ns violation into a 0.30 ns margin on paper while the hardware still fails.

    Interview

    Likely probes: the slack sign convention and what the critical path is.

    • Slack is required minus arrival; negative slack is a violation of that magnitude.

    • The critical path has the worst slack, not necessarily the most cells.

    • Two paths share one clock but can have different required times when setup values differ.

    Check yourself A path arrives at 2.90 ns with a required time of 3.60 ns. A second path arrives at 3.90 ns. What are the slacks, and which path is critical?

    The first slack is +0.70 ns and the second is -0.30 ns. The second path is critical because its slack is worse.

    Check yourself Required time drops by 0.50 ns while arrival stays fixed. How does the slack change?

    Slack falls by exactly 0.50 ns. Slack moves one-for-one with either term.

    Related topics

    • Setup, Hold and Clock-to-Q

    • SDC for Synthesis

    • Setup, Hold and Slack

    Previous

    42 / 139

    Next: Setup, Hold and Clock-to-Q

    Up next

    Up nextSetup, Hold and Clock-to-Q

    Sign in to save progress

    Practice this lessonReport an error

    See also

    • Cell Delay Models
    • Wire Delay at Synthesis Time
    • A Static Timing Calculator