A synthesis tool elaborates the RTL into a generic network first. It then simplifies that network and maps it onto library cells.
Inference is the first step deciding hardware: flops, latches, muxes, adders, or memories. Each row below is one question with its precise answer.
Question | Precise answer | Follow-up probe | Common wrong answer |
|---|---|---|---|
What does a synthesis tool do between RTL and gates? | Elaboration builds the hierarchy, generic optimization simplifies the logic, and mapping covers it with library cells. | Where does a flip-flop appear in that chain? | It translates each RTL line into one gate. |
What RTL pattern infers a latch, and why? | A combinational block that leaves an output unassigned on some path must keep the old value, which is storage: a latch. | Show the two one-line fixes. | Any block without a clock infers a latch. |
Small register file: flops or a memory macro? | Small arrays map to flops while large ones map to memory macros past a size threshold that varies by tool and library. | What decides the threshold? | Any array becomes a memory macro. |
The classic trap is an incomplete branch in combinational logic. A second trap is an array whose size sits near the flop-to-memory boundary.
A third trap is an asynchronous control that was drawn as synchronous. Naming the inferred hardware is the whole answer.
Name the inferred hardware, then the rule behind it, then the number. Close with what would change the answer.
A latch. The missing case must hold the old value, so the tool infers storage.
Usually flops at that size, but the boundary varies. Confirm against the target flow rather than guessing.