Real synthesis work arrives as symptoms: timing fails after an RTL change, area grows after a feature, a latch appears, hold breaks after scan, equivalence fails, power runs too high. Each scenario here is worked the same way: symptoms, a ranked investigation, the fix, and the trade-off.
Symptom | First suspicion |
|---|---|
Setup fails after an RTL edit | Added logic depth on the failing path. |
Area jumps after a feature | Replicated or widened datapath logic. |
A latch appears; hold fails after scan | Incomplete assignment; scan skew and routing at fixed arrival. |
The netlist fails equivalence | The two sides come from different revisions. |
Power too high at the same timing | Activity higher than the estimate assumed. |
Lesson | What it covers |
|---|---|
Slack before and after, ranked causes, and the fix. | |
Area split in library units, with the fix and its cost. | |
An inferred latch and a scan hold violation, each priced. | |
Localizing one wrong gate with a brute-force proof. | |
Hand power estimate, then gating at the same timing. |
Diff the inputs: RTL, constraints, and library versions against the last green run. Blaming the tool before the diff wastes the investigation.