Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
  • Constraints and Timing15
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
  • Area, Power and Test14
  • Verification, ECO and Handoff15
  • Flows and Debugging15
  • Interview and Judgment11
    • Synthesis Interview Questions
    • Synthesis Design Scenarios
      • Timing Fails After an RTL Change
      • Area Blows Up After Enabling a Feature
      • A Latch Appears and a Hold Surprise After Scan
      • A Netlist Fails Equivalence
      • Power Too High at the Same Timing
Loading lesson

‹Interview and Judgment
  1. Topics
  2. Logic Synthesis
  3. Interview and Judgment
  4. Synthesis Design Scenarios

Part 9 · Interview and Judgment · Intermediate

Synthesis Design Scenarios

Open-ended scenarios worked as decisions with investigation and trade-offs.

  • 5topics
  • 5lessons

Real synthesis work arrives as symptoms: timing fails after an RTL change, area grows after a feature, a latch appears, hold breaks after scan, equivalence fails, power runs too high. Each scenario here is worked the same way: symptoms, a ranked investigation, the fix, and the trade-off.

Decision flow used by every scenario in this topic.
Every scenario moves from symptom to investigation to a priced fix.

Symptom

First suspicion

Setup fails after an RTL edit

Added logic depth on the failing path.

Area jumps after a feature

Replicated or widened datapath logic.

A latch appears; hold fails after scan

Incomplete assignment; scan skew and routing at fixed arrival.

The netlist fails equivalence

The two sides come from different revisions.

Power too high at the same timing

Activity higher than the estimate assumed.

Lesson

What it covers

Timing fails after an RTL change

Slack before and after, ranked causes, and the fix.

Area blows up after enabling a feature

Area split in library units, with the fix and its cost.

A latch and a hold surprise

An inferred latch and a scan hold violation, each priced.

A netlist fails equivalence

Localizing one wrong gate with a brute-force proof.

Power too high at the same timing

Hand power estimate, then gating at the same timing.

Check yourself Timing fails the day after an RTL change. What is the first step?

Diff the inputs: RTL, constraints, and library versions against the last green run. Blaming the tool before the diff wastes the investigation.

Interview

Carry one decision per lesson: quote the number, name the ranked cause, state the fix and its price. Timing quotes slack, area quotes library units, power quotes the hand estimate.

PreviousNext: Timing Fails After an RTL Change

Up next

Up nextTiming Fails After an RTL Change

Sign in to save progress

Practice this lessonReport an error

See also

  • Synthesis Interview Questions