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Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
  • Constraints and Timing15
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
  • Area, Power and Test14
  • Verification, ECO and Handoff15
  • Flows and Debugging15
  • Interview and Judgment11
    • Synthesis Interview Questions
    • Synthesis Design Scenarios
      • Timing Fails After an RTL Change
      • Area Blows Up After Enabling a Feature
      • A Latch Appears and a Hold Surprise After Scan
      • A Netlist Fails Equivalence
      • Power Too High at the Same Timing
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‹Synthesis Design Scenarios
  1. Topics
  2. Logic Synthesis
  3. Interview and Judgment
  4. Synthesis Design Scenarios
  5. Power Too High at the Same Timing

Part 9 · Interview and Judgment · Intermediate

Power Too High at the Same Timing

A hand power estimate over budget, then cut with gating at the same timing.

On this page

    The symptoms

    Timing passes but dynamic power estimates 6.24 mW against a 5.00 mW budget. The same netlist meets every timing corner, so the problem is activity, not speed.

    All power figures here use EXAMPLE parameters with the formula P = alpha x C x V^2 x f. No figure describes a real process or product.

    Term

    EXAMPLE value

    Meaning

    alpha

    0.30

    Average toggle probability per clock.

    C

    65 pF

    Total switched capacitance.

    V

    0.8 V

    Supply voltage.

    f

    500 MHz

    Clock frequency, unchanged by the fix.

    The investigation

    Break power down by block before gating anything. One block usually carries the excess while the rest match the estimate.

    Rank the causes by what moves the product alpha times C. Enables stuck on top the list after a feature lands.

    Rank

    Likely cause

    How to confirm

    1

    An enable held high so idle logic toggles

    Compare enable duty against the plan.

    2

    Extra clocked elements from the feature

    Count flops before and after.

    3

    Glitching from unbalanced reconvergent paths

    Compare simulated toggles per net.

    4

    Stronger drives than timing needs

    List drive strengths on passing paths.

    Estimating by hand

    Substitution gives 6.24 mW as built, which is 1.24 mW over budget. The program below rechecks every figure quoted here.

    Diagram
    P = alpha x C x V^2 x f (EXAMPLE parameters, not real silicon)
    as built: 0.30 x 65 pF x (0.8 V)^2 x 500 MHz
    = 0.30 x 65e-12 x 0.64 x 5e8
    = 0.30 x 20.8e-3 = 6.24e-3 W = 6.24 mW
    over budget = 6.24 - 5.00 = 1.24 mW
    over share = 1.24 / 5.00 = 0.248 = 24.8%
    gated alpha = 0.12: P = 0.12 / 0.30 x 6.24 = 2.496 mW
    saving = 6.24 - 2.496 = 3.744 mW = 60.0% of as built
    example.py
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    import sys
    
    ALPHA = 0.30
    C = 65e-12
    V = 0.8
    F = 5e8
    BUDGET = 5.00
    GATED_ALPHA = 0.12
    
    def close(got, want):
        return abs(got - want) < 1e-9
    
    p_built = ALPHA * C * V * V * F * 1000.0
    over = p_built - BUDGET
    over_pct = over / BUDGET * 100.0
    p_gated = GATED_ALPHA * C * V * V * F * 1000.0
    saving_pct = (p_built - p_gated) / p_built * 100.0
    
    bad = 0
    if not close(p_built, 6.24):
        bad = bad + 1
    if not close(over, 1.24):
        bad = bad + 1
    if not close(over_pct, 24.8):
        bad = bad + 1
    if not close(p_gated, 2.496):
        bad = bad + 1
    if not close(saving_pct, 60.0):
        bad = bad + 1
    if bad != 0:
        print("FAIL: power arithmetic broke on " + str(bad) + " checks")
        sys.exit(1)
    print("PASS: 6.24 mW over a 5.00 mW budget, gated to 2.496 mW")

    Fix and trade-off

    Gate the feature block so its effective alpha falls from 0.30 to 0.12. Timing is untouched because the clock rate and the paths stay the same.

    Gating costs its own enable logic, area, and verification. That price varies by design, so restate it per block rather than quoting a rule.

    Common pitfall

    Gating the clock without verifying the enable timing trades a power problem for a functional one. Prove the enable is glitch-free before closing power.

    Interview

    Likely probes: the estimate first, then the lever.

    • As-built power is 6.24 mW, which is 24.8 percent over the 5.00 mW budget.

    • Gating cuts alpha from 0.30 to 0.12, giving 2.496 mW at the same timing.

    • The saving is 3.744 mW, which is 60.0 percent of the as-built figure.

    Check yourself Alpha is 0.30, C is 65 pF, V is 0.8 V, and f is 500 MHz. What is P?

    6.24 mW. The product is 0.30 times 65e-12 times 0.64 times 5e8, which is 6.24e-3 W.

    Check yourself Gating moves alpha to 0.12 with C, V, and f unchanged. What is the new power and saving?

    2.496 mW. The saving is 3.744 mW, which is 60.0 percent of 6.24 mW.

    Related topics

    • First lesson: Timing fails after an RTL change

    • Clock gating and low power

    • Area, power, and timing trade-offs

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    See also

    • Timing Fails After an RTL Change
    • Area Blows Up After Enabling a Feature
    • A Latch Appears and a Hold Surprise After Scan