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Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
  • Constraints and Timing15
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
  • Area, Power and Test14
  • Verification, ECO and Handoff15
  • Flows and Debugging15
  • Interview and Judgment11
    • Synthesis Interview Questions
    • Synthesis Design Scenarios
      • Timing Fails After an RTL Change
      • Area Blows Up After Enabling a Feature
      • A Latch Appears and a Hold Surprise After Scan
      • A Netlist Fails Equivalence
      • Power Too High at the Same Timing
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‹Synthesis Design Scenarios
  1. Topics
  2. Logic Synthesis
  3. Interview and Judgment
  4. Synthesis Design Scenarios
  5. A Netlist Fails Equivalence

Part 9 · Interview and Judgment · Intermediate

A Netlist Fails Equivalence

A failing equivalence check localized to one gate with a brute-force proof.

On this page

    The symptoms

    The equivalence check fails between the RTL and the handed-off netlist. Simulation passed, so the divergence hides where the tests never looked.

    The failing cone is small: a 3-input function of a, b, and c. The program below exhausts all 8 input patterns against the golden function.

    Pattern group

    Golden y

    Netlist y

    Agrees

    a and b both 1 (2 patterns)

    1

    1

    Yes

    Otherwise, c is 1 (3 patterns)

    1

    0

    No

    Otherwise, c is 0 (3 patterns)

    0

    1

    No

    The investigation

    Confirm the two sides come from the same revision first. Most failures are version skew, not real logic bugs.

    Then localize with the counterexample: one failing pattern names the cone, and the cone names the gate. Rank the causes before editing.

    Rank

    Likely cause

    How to confirm

    1

    RTL and netlist from different revisions

    Compare version tags on both sides.

    2

    A hand edit applied to one side only

    Diff the cone against the last passing pair.

    3

    A mismatched parameter or constant

    Check parameter bindings in the cone.

    4

    An unmapped black box in the path

    List black boxes in the failing cone.

    Proving the single wrong gate

    Golden is (a and b) or c. The netlist built (a and b) or (not c), a single inversion. Six of eight patterns disagree, which is 75 percent.

    The program below counts the disagreements for the buggy and the fixed netlist. Zero disagreements is the bar for handoff.

    Diagram
    golden y = (a and b) or c; buggy y = (a and b) or (not c)
    when a and b are both 1, both give 1: 2 of 8 patterns agree
    otherwise c and not c always differ: 6 of 8 patterns disagree
    disagreement = 6 / 8 = 0.75 = 75%
    fixed y = (a and b) or c: 0 of 8 patterns disagree
    example.py
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    import sys
    
    def golden(a, b, c):
        return (a and b) or c
    
    def buggy(a, b, c):
        return (a and b) or (not c)
    
    def fixed(a, b, c):
        return (a and b) or c
    
    miss_buggy = 0
    miss_fixed = 0
    total = 0
    for n in range(8):
        a = (n >> 2) & 1
        b = (n >> 1) & 1
        c = n & 1
        total = total + 1
        if buggy(a, b, c) != golden(a, b, c):
            miss_buggy = miss_buggy + 1
        if fixed(a, b, c) != golden(a, b, c):
            miss_fixed = miss_fixed + 1
    
    bad = 0
    if total != 8:
        bad = bad + 1
    if miss_buggy != 6:
        bad = bad + 1
    if miss_fixed != 0:
        bad = bad + 1
    if bad != 0:
        print("FAIL: agreement count broke on " + str(bad) + " checks")
        sys.exit(1)
    print("PASS: buggy netlist differs on 6 of 8 patterns, fixed on 0")

    Fix and trade-off

    Fix the source side and re-run the full check, not just the failing cone. A local fix can move the divergence elsewhere.

    Full re-verification costs machine time on every fix. Incremental checks on the cone guide the debug, and the full run closes it.

    Common pitfall

    Waiving the failure because simulation passed confuses two different questions. Simulation samples behavior; equivalence proves it for every pattern.

    Interview

    Likely probes: version skew first, then localization.

    • Same revisions first: most failures are skew, not logic bugs.

    • One failing pattern names the cone; the cone names the gate.

    • Six of eight patterns disagree here, and the bar for handoff is zero.

    Check yourself Golden is (a and b) or c and the netlist is (a and b) or (not c). On how many patterns do they disagree?

    Six of eight. They agree only when a and b are both 1, which is 2 patterns.

    Check yourself The cone fix passes but the full check has not been re-run. Can the netlist hand off?

    No. Re-run the full check, since a local fix can move the divergence to another cone.

    Related topics

    • Next: Power too high at the same timing

    • Equivalence checking

    • Simulation-synthesis mismatch

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    See also

    • Timing Fails After an RTL Change
    • Area Blows Up After Enabling a Feature