Sequential questions test what storage the RTL implies. Reset style and enable style each leave a distinct mark on the netlist.
Question | Precise answer | Follow-up probe | Common wrong answer |
|---|---|---|---|
Synchronous versus asynchronous reset: what differs after synthesis? | An asynchronous reset reaches the flop reset pin and needs recovery timing; a synchronous reset joins the data cone with no recovery check. | Which style needs the recovery check? | They synthesize to the same netlist. |
What does a clock enable map to? | A feedback mux or a flop with an enable pin, depending on the library; gating the clock instead needs dedicated gating cells. | Why not gate the clock with an AND gate? | An enable always becomes a clock gate. |
Encoding and sharing questions test cost judgment. The better choice varies by design, so each answer names the trade.
Question | Precise answer | Follow-up probe | Common wrong answer |
|---|---|---|---|
One-hot versus binary state encoding: what decides? | One-hot tests one bit per state and suits small FSMs; binary uses fewer flops and suits many states. | How many flops does each use for 8 states? | One-hot is always faster. |
When does resource sharing help? | When two identical operators never run in the same cycle; one unit plus a mux replaces two units at the cost of the mux delay. | What undoes the saving? | Sharing identical operators always saves area. |
The worked split below uses stated EXAMPLE parameters. Pipelining trades added latency for a shorter period.
EXAMPLE parameters, all in ns: 3 blocks of 4.0 each, flop overhead 0.5, uncertainty 0.2
unpipelined arrival = 3 x 4.0 = 12.0
unpipelined period target = 12.0 + 0.5 + 0.2 = 12.7
3-stage pipeline: longest stage 4.0
pipelined period target = 4.0 + 0.5 + 0.2 = 4.7
cost: latency rises from 1 cycle to 3 cyclesBinary uses 3 flops and one-hot uses 8.
Two extra cycles of latency: 3 cycles instead of 1.