Dynamic power is activity times capacitance times voltage squared times frequency. All values below are stated EXAMPLE parameters.
EXAMPLE parameters: activity 0.2, capacitance 50 fF, voltage 0.8 V, frequency 500 MHz
P = alpha x C x V squared x f
= 0.2 x 50e-15 F x 0.64 x 5e8 Hz
= 0.2 x 50 x 0.64 x 5 x 1e-7 W
= 3.2e-6 W = 3.2 uW
second case: 0.1 x 100e-15 F x 1.0 x 1e8 Hz = 1.0e-6 W = 1.0 uW
EXAMPLE split of the 3.2 uW total: registers 50 percent, combinational 30 percent, clock network 20 percent
50 + 30 + 20 = 100Gating questions test when the saving is real. The program below proves the two quoted power numbers.
import sys
def power(alpha, c_ff, v, f_hz):
return alpha * (c_ff * 1e-15) * v * v * f_hz
def close(got, want):
return abs(got - want) < 1e-12
cases = [
(power(0.2, 50.0, 0.8, 5e8), 3.2e-6),
(power(0.1, 100.0, 1.0, 1e8), 1.0e-6),
]
for i in range(len(cases)):
got, want = cases[i]
if not close(got, want):
print("FAIL: case " + str(i + 1) + " got " + str(got) + " want " + str(want))
sys.exit(1)
print("PASS: power cases agree at 3.2 uW and 1.0 uW")Question | Precise answer | Follow-up probe | Common wrong answer |
|---|---|---|---|
Write the dynamic power formula and evaluate the EXAMPLE case. | P is activity times capacitance times voltage squared times frequency, giving 3.2 uW for the stated values. | Which term moves most if voltage drops 10 percent? | Power scales linearly with voltage. |
What must hold for clock gating to save power? | The gated registers must hold value while disabled, the enable must be glitch-free, and the tree must stay balanced; savings vary with activity. | What breaks with a plain AND gate on the clock? | Gating the clock always saves power. |
Scan questions test what test logic costs the function. Every scan flop carries a mux the functional path must pass.
Question | Precise answer | Follow-up probe | Common wrong answer |
|---|---|---|---|
What does scan insertion change in the netlist? | Each flop gains a scan mux on its data input, chained serially for shift, adding area and a test mode the function must ignore. | What does it cost in area terms? | Scan is free because test logic is removed later. |
Why does shift timing get its own check? | Shift runs the whole chain in one mode, so its path needs a dedicated constraint apart from the functional clock. | What fails if shift is left unconstrained? | Functional timing covers shift automatically. |
Voltage squared gives 0.81, so power falls about 19 percent.
Registers 50 percent plus combinational 30 percent plus clock network 20 percent, which is 100 percent.