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Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
  • Constraints and Timing15
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
  • Area, Power and Test14
    • Area, Power and Timing Trade-offs
      • The Three-Way Trade-Off
      • Dynamic Power Arithmetic
      • Leakage and Vt Mixing
      • Sizing and Duplication Cost
      • Fair Comparison and Pareto Filtering
    • Clock Gating and Low Power
    • DFT and Scan Insertion
  • Verification, ECO and Handoff15
  • Flows and Debugging15
  • Interview and Judgment11
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‹Area, Power and Timing Trade-offs
  1. Topics
  2. Logic Synthesis
  3. Area, Power and Test
  4. Area, Power and Timing Trade-offs
  5. The Three-Way Trade-Off

Part 6 · Area, Power and Test · Intermediate

The Three-Way Trade-Off

Area, power, and timing move together when one constraint changes.

On this page

    The three axes

    Area counts silicon: cells times their sizes in library units of the teaching library. Power counts energy per second at stated activity. Timing counts delay against the clock, read as slack.

    Slack is required time minus arrival time, in EXAMPLE nanoseconds. Positive slack meets the clock; negative slack misses it.

    Axis

    Tighter constraint looks like

    Tool answer

    Timing

    A shorter clock period.

    Faster cells, more parallelism, duplicated logic.

    Area

    A smaller cell budget.

    Slower cells, shared resources, compact structures.

    Power

    A lower milliwatt budget.

    Gated clocks, calmer activity, high-Vt cells.

    One change moves all three

    A tighter clock usually grows area and power: the tool sizes gates up and duplicates cones to meet it. The exact cost varies between tools and libraries.

    A tighter area bound usually slows the design and trims dynamic power: shared, smaller cells switch less capacitance but stretch delay.

    Change

    Area

    Power

    Timing

    Shorter clock target

    Up: faster, larger cells.

    Up: bigger gates switch more.

    Better, at a cost.

    Smaller area budget

    Down, by order.

    Down for dynamic power.

    Worse: slower, shared logic.

    Lower EXAMPLE voltage

    May grow to recover speed.

    Down quadratically.

    Worse: gates slow down.

    Power now, energy per task

    Power and energy answer different questions. Power is joules per second; energy per operation divides power by the operation rate.

    The calc block runs one EXAMPLE corner at two frequencies. Power doubles with frequency, but energy per cycle is unchanged.

    Diagram
    EXAMPLE parameters (not real figures): alpha = 0.2, C = 50 pF, V = 0.9 V
    at f = 1 GHz: P = 0.2 x 50e-12 x 0.81 x 1e9 = 0.0081 W = 8.1 mW
    energy per cycle = 0.0081 / 1e9 = 8.1e-12 J = 8.1 pJ
    at f = 2 GHz: P = 0.2 x 50e-12 x 0.81 x 2e9 = 0.0162 W = 16.2 mW
    energy per cycle = 0.0162 / 2e9 = 8.1e-12 J = 8.1 pJ
    power doubled, energy per operation is unchanged

    Common mistakes

    No transform always helps: every speedup has an area or power price that varies with the design. Distrust any claim that a trick is free.

    Common pitfall

    Ranking runs by one axis misleads. A smaller netlist that misses timing, or a faster one that breaks the power budget, is not the better run.

    Interview

    Likely probes: tracing one constraint change through all three axes.

    • A shorter clock grows area and power through sizing and duplication.

    • A smaller budget slows timing through sharing and smaller cells.

    • Energy per operation, not power alone, compares work done.

    Check yourself The clock target tightens and timing closes, but the power report grows. What paid for the timing?

    Larger, faster cells and duplicated logic. Timing was bought with area and power.

    Check yourself Two runs do the same work: 8.1 mW at 1 GHz and 16.2 mW at 2 GHz. Which uses less energy per operation?

    Neither. Both cost 8.1 pJ per cycle, so the energy per operation ties.

    Related topics

    • Next: Dynamic Power Arithmetic

    • See also: Timing Driven Synthesis

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    See also

    • Leakage and Vt Mixing
    • Sizing and Duplication Cost
    • Fair Comparison and Pareto Filtering