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Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
  • Constraints and Timing15
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
  • Area, Power and Test14
    • Area, Power and Timing Trade-offs
      • The Three-Way Trade-Off
      • Dynamic Power Arithmetic
      • Leakage and Vt Mixing
      • Sizing and Duplication Cost
      • Fair Comparison and Pareto Filtering
    • Clock Gating and Low Power
    • DFT and Scan Insertion
  • Verification, ECO and Handoff15
  • Flows and Debugging15
  • Interview and Judgment11
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‹Area, Power and Timing Trade-offs
  1. Topics
  2. Logic Synthesis
  3. Area, Power and Test
  4. Area, Power and Timing Trade-offs
  5. Leakage and Vt Mixing

Part 6 · Area, Power and Test · Intermediate

Leakage and Vt Mixing

Leakage at concept level, Vt mixing, and leakage recovery after timing closure.

On this page

    Leakage at concept level

    Leakage flows even when nothing toggles: gates leak a small current at the supply voltage. The EXAMPLE model is linear: P_leak = N x I_gate x V, with a stated EXAMPLE current per gate.

    This model is a teaching stand-in, not a device model. Real leakage varies with process, voltage, and temperature, so every number here is labelled EXAMPLE.

    Symbol

    Meaning

    EXAMPLE value

    N

    Gate count.

    1000000

    I_gate

    Leakage current per gate.

    10 nA, low-Vt

    V

    Supply voltage.

    0.9 V

    P_leak

    N x I_gate x V.

    9 mW

    Threshold voltage mixing

    Low-Vt cells switch fast and leak most. High-Vt cells leak far less but switch slower.

    Mixing uses each where it pays: low-Vt on timing-critical paths, high-Vt everywhere else. The mix keeps the clock while cutting the leak.

    Cell flavour

    Speed

    Leakage

    Where it goes

    Low-Vt

    Fast.

    High: 10 nA per gate.

    Critical paths only.

    High-Vt

    Slower.

    Low: 2 nA per gate.

    All non-critical logic.

    Leakage recovery

    Recovery runs after timing closes: it swaps low-Vt cells on paths with spare slack for high-Vt ones. Each swap keeps slack non-negative and trims leakage.

    The calc block works a 30/70 mix. Average current falls from 10 nA to 4.4 nA per gate, and leakage falls from 9 mW to 3.96 mW.

    Diagram
    EXAMPLE concept model (not real figures): P_leak = N x I_gate x V
    all low-Vt: N = 1000000, I = 10 nA, V = 0.9 V
    P = 1e6 x 10e-9 x 0.9 = 1e6 x 9e-9 = 9e-3 W = 9 mW
    mixed: 30% low-Vt at 10 nA, 70% high-Vt at 2 nA
    average I = 0.3 x 10 + 0.7 x 2 = 3 + 1.4 = 4.4 nA
    P = 1e6 x 4.4e-9 x 0.9 = 1e6 x 3.96e-9 = 3.96e-3 W = 3.96 mW
    saving = 9 - 3.96 = 5.04 mW, 5.04 / 9 = 0.56 = 56%
    example.py
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    import sys
    
    def leak(n, i_gate, v):
        return n * i_gate * v
    
    all_low = leak(1000000, 10e-9, 0.9)
    avg_i = 0.3 * 10e-9 + 0.7 * 2e-9
    mixed = leak(1000000, avg_i, 0.9)
    all_high = leak(1000000, 2e-9, 0.9)
    
    checks = [
        (all_low, 0.009),
        (mixed, 0.00396),
        (all_high, 0.0018),
        ((all_low - mixed) / all_low, 0.56),
    ]
    
    for i in range(len(checks)):
        got, want = checks[i]
        if abs(got - want) > 1e-9:
            print("FAIL: check " + str(i + 1) + " got " + str(got) + " want " + str(want))
            sys.exit(1)
    
    print("PASS: leakage model agrees with hand arithmetic on 4 checks")

    Common mistakes

    Blanket high-Vt replacement breaks timing on critical paths. Recovery must recheck slack after every swap, since gains vary with available slack.

    Common pitfall

    Cutting leakage on a path with no spare slack just moves the violation. Swap only where slack stays non-negative, and re-time the whole design after.

    Interview

    Likely probes: why mixing beats one flavour, and what recovery checks.

    • Low-Vt buys speed where slack is tightest; high-Vt saves leakage everywhere else.

    • Recovery swaps low-Vt for high-Vt only on paths with spare slack.

    • The EXAMPLE mix saves 5.04 mW, which is 56% of the all-low-Vt leakage.

    Check yourself The mixed design leaks 3.96 mW against 9 mW all low-Vt. What is the saving as a fraction?

    5.04 mW saved out of 9 mW, which is 0.56 or 56%.

    Check yourself Why not use high-Vt cells everywhere?

    They are slower, so critical paths would miss the clock. Speed is needed exactly where slack is tightest.

    Related topics

    • Next: Sizing and Duplication Cost

    • See also: Cell Libraries and Liberty

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    See also

    • The Three-Way Trade-Off
    • Fair Comparison and Pareto Filtering