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Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
  • Constraints and Timing15
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
  • Area, Power and Test14
    • Area, Power and Timing Trade-offs
      • The Three-Way Trade-Off
      • Dynamic Power Arithmetic
      • Leakage and Vt Mixing
      • Sizing and Duplication Cost
      • Fair Comparison and Pareto Filtering
    • Clock Gating and Low Power
    • DFT and Scan Insertion
  • Verification, ECO and Handoff15
  • Flows and Debugging15
  • Interview and Judgment11
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‹Area, Power and Timing Trade-offs
  1. Topics
  2. Logic Synthesis
  3. Area, Power and Test
  4. Area, Power and Timing Trade-offs
  5. Dynamic Power Arithmetic

Part 6 · Area, Power and Test · Intermediate

Dynamic Power Arithmetic

Dynamic power from P = alpha C V squared f with worked EXAMPLE numbers.

On this page

    One formula

    Dynamic power is P = alpha x C x V squared x f. Every symbol below is a stated EXAMPLE parameter, never a real-process figure.

    Alpha is the fraction of capacitance toggling per cycle. C is the switched capacitance, V the supply, and f the clock rate.

    Symbol

    Meaning

    EXAMPLE value

    alpha

    Activity: toggles per cycle as a fraction.

    0.2

    C

    Switched capacitance.

    50 pF

    V

    Supply voltage.

    0.9 V

    f

    Clock frequency.

    1 GHz

    P

    alpha x C x V^2 x f.

    8.1 mW

    A worked EXAMPLE

    Substitute step by step and keep the units. The calc block below is the reference the program rechecks.

    Diagram
    EXAMPLE parameters (not real figures): alpha = 0.2, C = 50 pF, V = 0.9 V, f = 1 GHz
    V^2 = 0.9 x 0.9 = 0.81
    C x f = 50e-12 x 1e9 = 0.05
    P = 0.2 x 0.05 x 0.81 = 0.2 x 0.0405 = 0.0081 W = 8.1 mW
    half voltage (V = 0.45 V): V^2 = 0.2025
    P = 0.2 x 0.05 x 0.2025 = 0.002025 W = 2.025 mW = 0.25 x 8.1 mW
    gated activity (alpha = 0.05): P = 0.05 x 0.05 x 0.81 = 0.002025 W = 2.025 mW
    double frequency (f = 2 GHz): C x f = 0.1, P = 0.2 x 0.1 x 0.81 = 0.0162 W = 16.2 mW

    What each lever does

    Voltage is quadratic: halving it quarters power, before timing is considered. Activity and frequency are linear: halving either halves power.

    Capacitance follows the netlist: smaller cells and fewer toggled nets lower C. That is where synthesis earns its savings, and results vary by design.

    Lever

    Scaling

    EXAMPLE effect on 8.1 mW

    Halve voltage

    Quadratic.

    2.025 mW, one quarter.

    Quarter activity

    Linear.

    2.025 mW, one quarter.

    Double frequency

    Linear.

    16.2 mW, double.

    A runnable checker

    The program below recomputes every hand-worked number from the same EXAMPLE parameters. Its five self-checks pin the base case, the voltage, activity, and frequency variants, and the quarter-power ratio.

    example.py
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    import sys
    
    def dyn_power(alpha, c_f, v, f_hz):
        return alpha * c_f * v * v * f_hz
    
    C = 50e-12
    checks = [
        (dyn_power(0.2, C, 0.9, 1e9), 0.0081),
        (dyn_power(0.2, C, 0.45, 1e9), 0.002025),
        (dyn_power(0.05, C, 0.9, 1e9), 0.002025),
        (dyn_power(0.2, C, 0.9, 2e9), 0.0162),
        (dyn_power(0.2, C, 0.45, 1e9) / dyn_power(0.2, C, 0.9, 1e9), 0.25),
    ]
    
    for i in range(len(checks)):
        got, want = checks[i]
        if abs(got - want) > 1e-9:
            print("FAIL: check " + str(i + 1) + " got " + str(got) + " want " + str(want))
            sys.exit(1)
    
    print("PASS: dynamic power agrees with hand arithmetic on 5 checks")

    Common pitfall

    Quoting milliwatts without alpha, C, V, and f states nothing. The same netlist at different activity is a different power number.

    Interview

    Likely probes: units of each term and which lever moves most.

    • Alpha, C, V, and f multiply to watts: fraction times farads times volts squared times hertz.

    • Voltage is quadratic, so it dominates when timing allows the slowdown.

    • Activity is the honest lever in synthesis: gating and quiet datapaths lower alpha.

    Check yourself Voltage halves while the rest holds. What happens to dynamic power?

    It quarters. The V squared term goes from 0.81 to 0.2025, so 8.1 mW becomes 2.025 mW.

    Check yourself All five program checks pass. What does that prove?

    The code agrees with the hand arithmetic. It leaves open whether the EXAMPLE parameters match any real design.

    Related topics

    • Next: Leakage and Vt Mixing

    • See also: Clock Gating and Low Power

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    See also

    • Sizing and Duplication Cost
    • Fair Comparison and Pareto Filtering