Sizing up a gate

Sizing swaps a cell for a stronger, larger sibling that drives its load faster. The faster arrival costs area and switched capacitance, hence power.

The trade is local and bounded: it helps the paths it touches and taxes the power budget. Whether it closes timing varies with load and library.

Duplicating logic to cut load

Duplication copies a cone so each copy drives fewer sinks. Each sink sees less load, so arrivals improve, but every copy adds its full area and power.

The script below proves the cost in a synthesis tool: the same addition written twice stays two add cells after the share pass, as the assertion pins. Each copy is paid in full.

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read_verilog <<EOV
module top(input [7:0] a, b, output [8:0] y, z);
assign y = a + b;
assign z = a + b;
endmodule
EOV
hierarchy -check -top top
proc
share
select -assert-count 2 t:$add
log PASS: two identical 8-bit adds stay two add cells after share

A worked area cost

Areas below are library units of the fictional teaching library course.lib, not a real process. The cone is one AOI21 plus one MUX2.

Sharing keeps one cone; duplicating it for two sinks doubles the cone. The calc block prices the copy.

teaching library course.lib areas in library units: AOI21 = 3, MUX2 = 5
shared cone: one AOI21 + one MUX2 = 3 + 5 = 8 units
duplicated cone (one copy per sink): 2 x 8 = 16 units
extra cost = 16 - 8 = 8 units, 8 / 8 = 1.00 = +100% area for that cone

Common mistakes

Duplication without load relief buys nothing: two copies driving the same heavy net cost area for no timing gain. Always check what the copy unloads.

Related topics

• Next: Fair Comparison and Pareto Filtering

• See also: Technology Mapping