A full adder adds three bits: a, b, and a carry-in. It produces a sum bit and a carry-out.
The sum is odd parity, and the carry is majority. That gives s = a ^ b ^ cin and cout = (a & b) | (cin & (a ^ b)).
a | b | cin | s | cout |
|---|---|---|---|---|
0 | 0 | 0 | 0 | 0 |
0 | 0 | 1 | 1 | 0 |
0 | 1 | 0 | 1 | 0 |
0 | 1 | 1 | 0 | 1 |
1 | 0 | 0 | 1 | 0 |
1 | 0 | 1 | 0 | 1 |
1 | 1 | 0 | 0 | 1 |
1 | 1 | 1 | 1 | 1 |
An N-bit ripple-carry adder uses N full adders. The carry-out of bit i feeds the carry-in of bit i plus 1.
Delay grows linearly: N carry stages. Area grows linearly too: N full adders plus no extra control.
The calc block below uses EXAMPLE stage delays, not measured silicon. Both rows follow one multiplication each.
EXAMPLE parameters (not measured silicon): one carry stage = 3 delay units
4-bit ripple: 4 x 3 = 12 units
16-bit ripple: 16 x 3 = 48 units
ratio: 48 / 12 = 4 for 4x width (linear growth)12 units and 48 units. The ratio is 4 for 4x width, which is linear growth.
Carry-out alone cannot say. Signed overflow needs top-bit carry-in XOR carry-out; 200 and 100 are not valid signed 8-bit values anyway.