Each upper block is built twice: once assuming carry-in 0, once assuming 1. Both versions compute while the lower block settles.
The true carry-in then picks the right version through a mux. The mux delay replaces the wait for the full lower ripple.
With uniform block size k, each block ripples k stages and each boundary adds one mux stage. Smaller blocks ripple less but cross more muxes.
The table below uses EXAMPLE costs for an 8-bit adder. Variable block sizes, growing toward the top bit, do better, and the best split varies by library.
Block size k | Ripple part (EXAMPLE) | Mux stages (EXAMPLE) | Total (EXAMPLE) |
|---|---|---|---|
2 | 2 x 3 = 6 | 3 x 2 = 6 | 12 |
4 | 4 x 3 = 12 | 1 x 2 = 2 | 14 |
8 | 8 x 3 = 24 | 0 | 24 |
Selection costs one mux per sum bit plus the select wiring. Area approaches twice the ripple for many blocks (one extra block per upper group, plus the select muxes).
EXAMPLE parameters (not measured silicon): one carry stage = 3 units, one mux stage = 2 units
8-bit carry-select, block size 4: 4 x 3 + 2 = 12 + 2 = 14 units
8-bit ripple: 8 x 3 = 24 units
saving: 24 - 14 = 10 unitsBlock size 4 gives 12 + 2 = 14 units. Size 8 is a plain ripple at 24 units with no mux.
Upper muxes wait for selects from below, so upper blocks can afford longer ripples. Growing sizes match ripple arrival to select arrival.