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Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
  • Constraints and Timing15
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
    • Adders and Carry Structures
      • Ripple-Carry Adders
      • Carry-Lookahead Adders
      • Carry-Select Adders
      • Prefix Adders
      • The Plus Operator and Carry-Save Addition
    • Multipliers and Compressors
    • Resource Sharing and Arithmetic Inference
  • Area, Power and Test14
  • Verification, ECO and Handoff15
  • Flows and Debugging15
  • Interview and Judgment11
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‹Adders and Carry Structures
  1. Topics
  2. Logic Synthesis
  3. Datapath Synthesis
  4. Adders and Carry Structures
  5. Carry-Lookahead Adders

Part 5 · Datapath Synthesis · Intermediate

Carry-Lookahead Adders

Generate and propagate signals that compute all carries in parallel groups.

On this page

    Generate and propagate

    Each bit declares two facts: generate g = a & b, and propagate p = a ^ b. Generate makes a carry locally; propagate passes an incoming carry through.

    The carry recurrence is c[i+1] = g[i] + p[i] c[i], with + as OR and juxtaposition as AND. Unrolling it removes the wait for lower bits.

    Signal

    Formula

    Meaning

    g[i]

    a[i] & b[i]

    Bit i creates a carry regardless of carry-in.

    p[i]

    a[i] ^ b[i]

    Bit i passes its carry-in to carry-out.

    c[i+1]

    g[i] + p[i] c[i]

    Carry-out from local facts plus the incoming carry.

    Group carries

    A 4-bit block unrolls the recurrence fully. Every carry is a sum of products of g, p, and the block carry-in.

    Notation below: + is OR, juxtaposition is AND. Each product covers one way the carry can arise.

    Diagram
    4-bit lookahead block with carry-in c0:
    c1 = g0 + p0 c0
    c2 = g1 + p1 g0 + p1 p0 c0
    c3 = g2 + p2 g1 + p2 p1 g0 + p2 p1 p0 c0
    c4 = g3 + p3 g2 + p3 p2 g1 + p3 p2 p1 g0 + p3 p2 p1 p0 c0
    s[i] = p[i] ^ c[i] for i = 0..3

    Depth against fan-in

    The block carry uses two AND-OR levels instead of four ripple stages. But the widest product has five inputs, so wider blocks slow each gate.

    Designs group 4 bits at a time and add a second lookahead level across groups. Group size trades fewer levels against wider, slower gates, and the best size varies by library.

    Diagram
    EXAMPLE parameters (not measured silicon): one AND-OR level = 1 unit, one ripple carry stage = 2 units
    16-bit two-level lookahead, 4-bit groups: pg 1 + block 2 + top 2 + sum 1 = 6 units
    16-bit ripple: 16 x 2 = 32 units

    Common mistakes

    Common pitfall

    Widening one block to 16 bits to kill the second level. The 16-input products exceed practical fan-in, so the gates slow down and the win evaporates; keep groups narrow and add levels.

    Interview

    Likely probes: the recurrence and the grouping trade.

    • Carry recurrence is c[i+1] = g[i] + p[i] c[i] from per-bit generate and propagate.

    • A 4-bit block reaches c4 in two AND-OR levels with at most five-input products.

    • Wider groups cut levels but raise fan-in, so group size varies by library.

    Check yourself With g = 0110 and p = 1111 from bit 3 to bit 0 and c0 = 0, what is c4?

    c4 = g3 + p3 g2 + p3 p2 g1 + p3 p2 p1 g0 + p3 p2 p1 p0 c0 = 0 + 1 + 1 + 0 + 0 = 1. Bits 1 and 2 generate and the upper bits propagate.

    Check yourself The 16-bit EXAMPLE gives 6 units against 32 for ripple. What assumption could overturn that win?

    The unit costs are EXAMPLE parameters. A library with slow wide gates or fast carry chains changes both rows, so the comparison must be remeasured.

    Related topics

    • Carry-select adders

    • See also: Technology Mapping

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    See also

    • Prefix Adders
    • The Plus Operator and Carry-Save Addition