Course map
- 4 lessons
Starts with How to Use This Course
- 14 lessons
Starts with Why UVM Exists: History and Goals
- 26 lessons
Starts with Why Phases Exist
- 15 lessons
Starts with The Factory: Swapping Classes Without Editing the Env
- 13 lessons
Starts with Who Calls, Who Implements: Ports, Exports and Imps
- 21 lessons
Starts with Item vs Driver Boundary: What Belongs Where
- 21 lessons
Starts with What an Agent Owns, and What It Shows the World
- 11 lessons
Starts with The Environment and Its Config Object
- 21 lessons
Starts with Expected vs Actual: The Two-Stream Model
- 22 lessons
Starts with Why a Register Model: Desired, Mirrored and the DUT
- 13 lessons
Starts with Callbacks Done Right
- 10 lessons
Starts with The UVM Debug Toolkit
- 47 lessons
Starts with How to Use This Course
- 10 lessons
Starts with Gate-Level Simulation with a UVM Bench
- 32 lessons
Starts with Writing a Testplan from the Spec
About this course
Choose a learning path
Senior DV interviews rarely ask what an objection is. They ask why your test passed with a word missing, what changes when your block bench goes into a chip, and how you would find what is holding a hung test open. This course teaches UVM for those questions. Every lesson builds on one running testbench for a small DMA, shows real logs from it, breaks it on purpose, and ends with the question an interviewer would ask.
Start with [Start here](uvm/start-here). It takes under an hour and explains how the lessons work, what the DMA does, how to run the bench for free, and which UVM dialect the course writes.
What you will be able to do
Explain every core mechanism, from phases and the factory to sequences and the register layer, starting from the problem it solves.
Build, run and debug a complete UVM bench, and tell real failure stories from it.
Design a testbench and a testplan for a block, and say how both scale to a chip.
Write code that compiles on UVM 1.2 and IEEE 1800.2, and know where they differ.
The learning map
Show how the course is organised
Part | Topics | Lessons | What it covers |
|---|---|---|---|
– | 4 | How to use the course, the DMA design, running UVM on EDA Playground, and UVM 1.2 versus IEEE 1800.2. | |
2 | 14 | What UVM is, components and objects, item utilities, testplans, and the complete DMA bench, layered and reused. | |
4 | 26 | Build, connect and run; objections and end of test; drain time, domains, reset, and phase debug. | |
2 | 15 | Registration, overrides, and config_db: precedence, wildcards, and typed configuration. | |
2 | 13 | Ports, exports and imps, analysis broadcast, FIFOs, and TLM-2 sockets. | |
3 | 21 | Items and constraints, the driver handshake, field macros, and virtual sequences. | |
4 | 21 | Agent structure, active and passive reuse, VIP design, and error injection. | |
2 | 11 | Base tests, scenario inheritance, overrides from tests, and test selection. | |
3 | 21 | Scoreboards and reference models, in-order and out-of-order matching, and functional coverage. | |
3 | 22 | Register blocks, maps, the mirror, prediction, and frontdoor and backdoor access. | |
3 | 13 | Callbacks, plusargs, seeds and random stability, compatibility, and performance. | |
2 | 10 | The debug toolkit and playbooks for hangs, mismatches and false passes, then regression and sign-off. | |
3 | 10 | Optional: simulations for sign-off, safety, acceleration and models, and verification beyond simulation. | |
4 | 32 | Verification architecture, SVA and formal, debug playbooks, and interview answers. |
Two ways to use it
Read in order if you have a few weeks. Each part extends the bench from the last, so by the end you have built a complete environment with backpressure, a register model and a set of tests you can explain line by line.
Jump to a topic if your interview is close. Read Your first UVM testbench first, then go straight to the part you need; every lesson links back to the bench code it uses. How to use this course has a two-week plan.
How the examples are checked
The DMA bench is a complete UVM testbench, built and run with Verilator and the open-source UVM library. The logs in lessons come from those runs; it also runs on EDA Playground with UVM 1.2.
Every listing is written to the subset UVM 1.2 and IEEE 1800.2 both accept. Fragments are marked
// snippetand are never shown with invented output.Plain-SystemVerilog models of mechanisms carry their own self-check and print a
PASSline when the course's checks run them.
Check yourself Before starting: what keeps a run phase alive after all sequences finish, and what swaps a component's type without editing the testbench?
Objections hold the phase open, and factory overrides swap types at create time. Phases and Factory and Config build both ideas from scratch, and the DMA bench's drain and truncate tests show them running.