The rest of this course builds and debugs one UVM bench on RTL. On a real chip that is the centre of the work, not all of it. After the RTL regression is green, the same bench runs on the netlist and with the power intent; safety-critical parts go through fault campaigns; the slowest tests move to an emulator or an FPGA; and formal tools prove properties that no amount of random simulation can close. Senior interviews probe exactly these activities, because they separate engineers who have taken a chip to tape-out from those who have only run a block regression.
Explain what gate-level, reset and X-propagation, and power-aware simulations find that RTL simulation misses, and adapt a UVM bench to each.
Describe how functional safety, emulation and FPGA prototyping, multi-language benches and mixed-signal models change the verification plan.
Decide where formal verification and assertion IP replace or support simulation, and where newer automation fits.
Place each activity on a project timeline and say what evidence it contributes to sign-off.
Each topic below takes one part of that picture. They can be read in any order, but the first topic sets up the vocabulary (X, netlists, power intent) that the other two use, and inside it the reset lesson comes before the GLS lesson if X-optimism is new to you.
Topic | What it covers |
|---|---|
Gate-level simulation with a UVM bench, reset and X-propagation verification, and power-aware simulation with UPF. | |
Functional safety verification, emulation and FPGA prototyping, multi-language benches, and mixed-signal verification. | |
Formal verification alongside simulation, assertion VIP and bind, and machine learning in DV. |