By the time a block's RTL regression is green, most of its functional bugs are gone. The bugs that remain hide in places RTL simulation cannot see: an unknown value that an if statement quietly turned into a clean 0, a flop that synthesis renamed so your probe no longer compiles, a power domain that leaks X into the always-on logic when it switches off. This topic covers the three simulations a chip runs before tape-out to find them, and how the same UVM bench is adapted for each.
Explain why gate-level simulation still exists next to equivalence checking and STA, plan a reduced GLS test list, and adapt a UVM bench to a netlist (probes, binds, driver timing, timing checks).
Show how RTL simulation hides X (X-optimism) and gates exaggerate it (X-pessimism), verify reset sequencing, and write no-X checks that actually fire.
Read a UPF power intent file, describe what a power-aware simulator does with it, and build the UVM pieces of a power-aware bench: a power-control agent, power-state sequences, isolation and retention checks, and transition coverage.
Lesson | The question it answers |
|---|---|
Equivalence checking already proved the netlist matches the RTL. Why run it again, and what breaks in the bench when you do? | |
Why can an RTL regression pass while the netlist powers up full of X, and which checks catch it early? | |
What does the simulator do when a domain turns off, and what must the bench check around it? |